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[1] Xuelong Shi,Allen Fung, Stephen Hsu, Zongyu Li, Tim Nguyen, Robert Socha, Will Conley, Mircea Dusa, "Dual damascene photo process using negative tone resist", Proceedings of SPIE Vol.3999 (2000) [2] Mark T. Bohr, "Interconnect scaling-the real limiter to high performance ULSI", IEEE IEDM, 10-13 DEC. pp.241-244 (1995) [3]Burn J. Lin, “The k3 coefficient in nonparaxial λ/NA scaling equations for resolution, depth of focus, and immersion lithography”, Society of Photo-Optical Instrumentation Engineers, pp.7-12 (2002) [4]Ban P. Wang, Anurag Mittal, Yu Cao, Greg Starr, “Nano-CMOS circuit and physical design”, John Wiley & Sons Inc. US. (2004) [5]Bruce W. Smith, “Mutual optimization of resolution enhancement techniques”, J. Microlith Microfabrication, Microsyst. 1, 95 (2002) [6]Yong-Ho Oh, Jai-Cheol Lee, and Sungwoo Lim ” Resolution enhancement through optical proximity correction and stepper parameter optimization for 0.12-μm mask pattern” Proc. SPIE Int. Soc. Opt. Eng. 3679, 607 (1999) [7] Puneet Gupta, Andrew B. Kahng, Swamy Muddu, Sam Nakagawa, Chul-Hong Park, “Modeling OPC complexity for design for manufacturability”, Proc. SPIE Vol.5992, p. 612-622, 25th Annual BACUS Symposium on Photomask Technology; J. Tracy Weed, Patrick M. Martin; Eds. (Nov 2005) [8]Emiko Sugiura, Hisashi Watanabe, Tadashi Imoriya, Yoshihiro Todokoro, “Fabrication and pattern transfer of optical proximity correction(OPC) mask”, SPIE Vol.2254 Photomask and X-Ray Mask Technology, pp.183-192 (1994) [9] Eric S. Wu, Balu Santhanam, and S. R. J. Brueck, “General framework for 36 parameter optimization in imaging interferometric lithography”, J. Microlith Microfabrication, Microsyst. 4, 023009 (2005) [10]Marc D. Levenson, N. S. Viswanwthan, Eobert A. Simpson, “Improving resolution in photolithography with a phase-shifting mask”, IEEE Transactions on Electron Devices, vol. ed-29, No. 12 pp.1828-1836 (1982) [11]Marc D. Levenson, “What is a phase-shifting mask?”, SPIE Vol. 1496 10th Annual Symposium on Microlithography (1990) [12]B. J. Lin, “Off-axis illumination – Working principles and comparison with alternating phase-shifting masks”, SPIE Vol. 1927 Optical/Laser Microlithography VI (1993) [13]L. Arnaud, T. Berger, G. Reimbold, “Evidence of grain-boundary versus interface diffusion in electromigration experiments in copper damascene interconnects”, Journal of Applied Physics, Vol. 93 Issue 1, pp.192 (2003) [14]Stanley Wolf, “Introduction to dual damascene interconnect processes”, SILICON PROCESSING FOR THE VLSI ERA Vol. 4, pp. 674-679 Publisher: Lattice Press (2004). [15]P. Josh Wolf, “Overview of Dual Damascene Cu/Low-k Interconnect”, IITC workshop (2004) [16]Robert H. Havemann and James A. Hutchby, “High-Performance Interconnects: An Integration Overview”, PROCEEDINGS OF THE IEEE, Vol. 89, No. 5, May (2001) [17]Ogawa, E.T.; Ki-Don Lee; Blaschke, V.A.; Ho, P.S.,” Electromigration reliability issues in dual-damascene Cu interconnections” IEEE Transactions on Reliabilit, Volume 51, Issue 4, Page 403 – 419, Dec. 2002 [18]龍文安, “半導體微影技術”, 五南圖書出版公司, 台灣, pp. 270-293 (2004) [19]ASML product website: http://www.asml.com/asmldotcom/show.do?ctx=6717 [20]NIKON product website: http://www.ave.nikon.co.jp/pec_e/products/nsr.htm [21]Jos de Klerk, “Performance of a high NA, dual stage 193nm TWINSCANTM step & scan system for 80nm applications”, Optical Microlithography XVI, Anthony Yen, Editor, Proceedings of SPIE Vol. 5040 (2003) [22]ITRS Lithography (2006)
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