臺灣博碩士論文加值系統

近年來，隨著可攜式多媒體產業的快速發展，面對低功率的電路設計越來越受重視。然而，在製程技術的演進下，操作電壓也不斷降低，類比電路設計將直接面對信號動態範圍的減少和動態效能降低的問題，若欲提升電路效能來抑制雜訊與降低非線性造成的諧波失真，將需耗費更大的電流，使得功率消耗問題面臨挑戰。
此論文中，吾人使用台積電標準0.18微米互補式金氧半製程，設計一個十位元每秒取樣66.6百萬次，操作於單電源1.8伏特的管線式類比至數位轉換器，其架構採用8級1.5位元/級的轉換級，此低位元轉換級具有低雜訊和低功率消耗的優點，加上最後一級為快閃式轉換級，共九級；以修正後的運算放大器使用在取樣電路和乘法式數位至類比轉換器，並以四種不同規格之放大器來實現降低功率消耗的設計目標；同時在開關設計方面，使用電壓靴帶式電路讓開關的非線性問題降低，最後在所有級數的輸出經由數位誤差更正電路而得到十位元的數位輸出碼，此數位誤差更正電路可減輕比較器所需的精準度，使得比較器能夠容忍±125毫伏的偏壓誤差。此論文設計結果，在1MHz輸入信號頻率，其SFDR/SNR/SNDR為58.81dB/55.62dB/51.85dB，有效位元數為8.32bit，所需功率損耗為76.36mw，晶片面積為1mm2。

Recently, as portable multimedia develops rapidly, the low power issue for analog design is more and more important. However, with the advance of the deep submicron technique, for the analog design, we faces some problems that the decreases of signal dynamic range and dynamic performance, if we want to enhance the performance to suppress the noise and distortion which suffers from nonlinearity, we will make so large current that the low power design has a challenge.
In this thesis, we design a 10-bit 66.6MS/s pipelined Analog-to-Digital converter with TSMC 0.18μm CMOS 1P6M process at 1.8V supply, and adopt eight conversion stages which 1.5-bit per stage has low noise and low power dissipation advantages, there are all 9 stages. We use the modified op-amp architecture for S/H and MDAC circuit, and take four kind of different specifications for low power design. Simultaneously, for the switch design, we reduce the nonlinearity of the switch by using the voltage-bootstrapped circuit. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit, which can reduce the demand of the comparator and let it tolerate ±125mv of offset voltage. In this design result, when input signal frequency at 1MHz, we get SFDR/SNR/SNDR is 58.81dB/55.62dB/51.85dB, the effective number of bit(ENOB) is 8.32bit, total power dissipation is76.36mW, and total chip area is 1mm2.

目錄

誌謝……………………………………………………………………………
中文摘要……………………………………………………………………… Ⅰ
英文摘要……………………………………………………………………… Ⅱ
目錄…………………………………………………………………………… Ⅳ
圖目錄………………………………………………………………………… Ⅵ
表目錄………………………………………………………………………… Ⅸ

第一章 緒論 1
1.1 相關發展現況、應用與動機…………………………………… 1
1.2 論文組織………………………………………………………… 5

第二章 類比至數位轉換器的基礎理論……………………………………6
2.1 類比至數位轉換器效能特性…………………………………… 6
2.1.1 靜態特性…………………………………………………6
2.1.1.1 分別的非線性誤差與整體的非線性誤差 7
2.1.1.2 偏移誤差……………………………………7
2.1.1.3 增益誤差……………………………………8
2.1.1.4 單調性………………………………………8
2.1.2 動態特性………………………………………8
2.1.2.1 信號雜訊比…………………………………9
2.1.2.2 信號雜訊失真比……………………………10
2.1.2.3 解析度………………………………………10
2.1.2.4 無寄生動態範圍……………………………10
2.1.2.5 動態範圍……………………………………11
2.1.2.6 有效解析度頻寬……………………………11
2.2 高速類比至數位轉換器架構……………………………12
2.2.1 快閃式類比至數位轉換器……………………………12
2.2.2 兩階快閃式類比至數位轉換器…………………………13
2.2.3 管線式類比至數位轉換器………………………………14
2.3 管線式類比至數位轉換器之主要架構……………………16
2.3.1 每級位元數之考量………………………………………17
2.3.2 數位誤差更正電路………………………………………18
第三章 管線式類比至數位轉換器之非線性考量與全差動式大器之設計……21
3.1 非線性之考量………………………………………………22
3.1.1 開關之非線性……………………………………………22
3.1.2 運算放大器之非線性……………………………………26
3.1.3 電容不匹配之非線性……………………………………28
3.2 轉換級的規格需求與功率…………………………………28
3.2.1 運算放大器之需求………………………………………29
3.2.2 電容值之考量……………………………………………31
3.2.3 轉換級功率分布…………………………………………31
3.3 全差動式放大器之設計……………………………………33
3.3.1 兩級式運算放大器………………………………………34
3.3.2 共模回授電路……………………………………………38
3.3.3 模擬結果…………………………………………………38
3.3.4 低增益放大器……………………………………………40

第四章 管線式類比至數位轉換器之設計與模擬結果……………………42
4.1 取樣保持電路…………………………………………………………42
4.2 電壓靴帶式電路………………………………………………………45
4.3 1.5位元之轉換級……………………………………………………47
4.4 時脈產生器電路………………………………………………………51
4.5 暫存器與數位誤差更正電路…………………………………………52
4.6 偏壓電路………………………………………………………………54
4.7 電路佈局圖……………………………………………………………55
4.8 管線式類比至數位轉換器設計模擬結果……………………………57

第五章 結論……………………………………………………………………62

參考文獻…………………………………………………………………………64
附錄………………………………………………………………………………68

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