臺灣博碩士論文加值系統

在現今的積體電路中，因為高密度的邏輯閘分佈與高密度的導線連接，耦合效應亦即串音效應對電路的影響扮演越來越重要的地位。因此如何正確又快速地測試電路中的串音效應即是代表積體電路設計與測試的優勢。
在本篇論文中我們探討串音現象所造成的延遲問題。藉由分析電路中的訊號傳遞路徑去找出與串因延遲相關性。某些路徑會對串因延遲具有較高的敏感度，分析這些路徑可以得到所需要的延遲效應進而達到串音延遲測試。
藉由提出最長路徑搜尋演算法，去研究最長路徑與串音延遲的關連。並且利用電容來表現出耦合效應所產生的傳遞延遲。藉由此方法去模擬電路的串音延遲效應。最後再與佈局萃取出來的電容值重新模擬作驗證，完成串音延遲測試。

Because of increasing gate density and interconnects, the influence of coupling effects (cross-talk) on the recent integrated circuits are more and more seriously. Therefore, how to correctly and quickly evaluate the cross-talk effects in a circuit often represents the superiority of IC design and testing.
This thesis discussed the problems of cross-talk induced delay and find out the correlation between cross-talk and delay by analyzing the paths of signal transmission. Some paths are highly sensitive to cross-talk induced delay. To analyze these paths can gain the delay effects and then come to cross-talk induced delay testing.
This thesis proposed an algorithm of searching longest path to search the relationship between the longest path and cross-talk induced delay. Moreover, this thesis took advantage of capacitances to replace the transmission delay induced by coupling effects. By using this method to simulate the effects of cross-talk induced delay of the circuits. Pre-simulation, physical layout and post-simulation were presented to reveal that the feasibility and effectiveness of the proposed method.

論文目錄

圖目錄
表目錄
第一章 導論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 串音效應與電路模型分析 3
2.1 串音效應 3
2.2 串音雜訊延遲估算 4
2.3 電路延遲錯誤 6
2.4 電路延遲測試訊號 7
第三章 路徑導向串音測試 10
3.1 靜態分析 10
3.1.1 階層化 10
3.1.2 時脈視窗 11
3.1.3 靜態路徑 12
3.2 最長路徑搜尋 16
3.2.1 節點階層化 17
3.2.2 追溯搜尋 19
3.3 樣本電路之最長路徑分析 20
3.3.1 節點階層化分析 20
3.3.2 追溯搜尋分析 22
第四章 串音雜訊延遲錯誤模擬與分析 24
4.1 最長路徑延遲模擬 24
4.2 測試向量 24
4.3 錯誤模型 25
4.3.1 單一錯誤模型 26
4.3.2 雙重錯誤模型 26
4.3.3 多重錯誤模型 27
4.3.4 全錯誤模型 27
4.4 串音雜訊延遲錯誤模擬 27
4.4.1 單一錯誤模擬結果 27
4.4.2 雙重錯誤模擬結果 34
4.4.3 多重錯誤模擬結果 38
4.4.4 全錯誤模擬結果 42
4.5 佈局萃取模擬 43
4.5.1佈局萃取之單一錯誤模擬結果 44
4.5.2佈局萃取之雙重錯誤模擬結果 45
4.5.3佈局萃取之多重錯誤模擬結果 48
4.5.4佈局萃取之全錯誤模擬結果 50
4.6 標準電路模擬結果 52
第五章 結論與未來展望 53
參考文獻 54

圖目錄

圖2.1 電容耦合模型 4
圖2.2 多重耦合運作訊號 4
圖2.3 Elmore延遲計算範例電路 5
圖2.4 延遲錯誤示意圖 7
圖2.5 主要輸入端個數為三的電路 8
圖2.6 延遲測試訊號 9
圖3.1 邏輯閘階層化 11
圖3.2 時脈視窗的計算結果 12
圖3.3 靜態分析演算法流程圖 14
圖3.4 靜態電路分析 15
圖3.5 節點階層化 17
圖3.6 節點階層化流程圖 18
圖3.7 追溯搜尋流程圖 20
圖3.8 樣本電路 21
圖4.1 最簡單的延遲量模擬模型 25
圖4.2 各種錯誤模型 26
圖4.3 輸入向量為（U0，S0，S1，U0，U0，U1）的單一錯誤延遲量 29
圖4.4 輸入向量為（U0，S0，U1，S0，U0，U1）的單一錯誤延遲量 30
圖4.5 輸入向量為（U0，U0，U1，U0，U0，U1）的單一錯誤延遲量 31
圖4.6 輸入向量為（S1，U1，U1，U1，U1，U1）的單一錯誤延遲量 32
圖4.7 輸入向量為（S0，U0，U1，U0，U1，U0）的單一錯誤延遲量 33
圖4.8 輸入向量為（S0，U1，U0，S0，U1，U0）的單一錯誤延遲量 34
圖4.9 輸入向量為（U0，S0，S1，U0，U0，U1）的雙重錯誤延遲量 36
圖4.10 輸入向量為（U0，U0，S1，U0，U0，U1）的雙重錯誤延遲量 37
圖4.11 輸入向量為（U0，U0，U1，U0，U1，S1）的雙重錯誤延遲量 38
圖4.12 輸入向量為（U0，S0，S1，U0，U0，U1）的多重錯誤延遲量 40
圖4.13 輸入向量為（U0，U0，U1，U0，U0，U1）的多重錯誤延遲量 41
圖4.14 輸入向量為（U0，S0，S1，U0，U0，U1）的全錯誤延遲量 43
圖4.15 樣本電路佈局圖 43

表目錄

表4.1 樣本電路之單一錯誤事前模擬結果 28
表4.2 樣本電路之雙重錯誤事前模擬結果 35
表4.3 樣本電路之多重錯誤事前模擬結果 39
表4.4 樣本電路之全錯誤事前模擬結果 42
表4.5 樣本電路佈局萃取之單一錯誤模擬結果 44
表4.6 樣本電路單一錯誤之事前模擬與佈局萃取事後模擬比較表 44
表4.7 樣本電路佈局萃取之雙重錯誤模擬結果 46
表4.8 樣本電路雙重錯誤之事前模擬與佈局萃取事後模擬比較表 47
表4.9 樣本電路佈局萃取之多重錯誤模擬結果 49
表4.10 樣本電路三重錯誤之事前模擬與佈局萃取事後模擬比較表 50
表4.11 樣本電路佈局萃取之全錯誤模擬結果 51
表4.12 樣本電路三重錯誤之事前模擬與佈局萃取事後模擬比較表 51
表4.13 標準電路之單一錯誤模擬結果 52

[1] K. T. Cheng, S. Dey, M. Rodgers, and K. Roy, “Test challenges for deep sub-micron technologies,” Proceedings of 37th Design Automation Conference, pp. 142-149, 2000.
[2] A. E. Zain and S. Chowdhury, “An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines,” Proceedings of Computed Aided Design Conference, pp. 443-448, 1992.
[3]H. You and M. Soma, “Crosstalk and transient analysis of highspeed interconnects and packages,” IEEE Trans. on Solid State Circuits, vol. 26, pp. 319-30, 1991.
[4] S. H. Choi, B.C. Paul, and K. Roy, “Dynamic noise analysis with capacitive and inductive coupling,” Design Automation Conference, Proceedings of ASP-DAC Asia and South Pacific and the 15th International Conference on VLSI Design, pp. 65-70, 2002.
[5] D. S. Gao, A. T. Yang, and S. M. Kang, “Modeling and simulation of interconnection delays and crosstalk in highspeed integrated circuits,” IEEE Trans. on Circuits and Systems, vol. 37, pp.1-9, 1990.
[6] A. Krstic, J. J. Liou, Y. M. Jiang, and K. T. Cheng, “Delay testing considering crosstalk-induced effects,” Proceedings of IEEE International Test Conference, pp. 558-567, 2001.
[7] K. T. Cheng and H. C. Chen, “Classification and identification of nonrobust untestable path delay faults,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, vol. 15, no.8, pp. 845-853, 1996.
[8] M. Becer and I. Hajj, “An analytical model for delay and crosstalk estimation with application to decoupling,” International Symposium Quality Electronic Design, pp.51-57, 2000.
[9] P. K. Chan, “An extension of elmore delay,” IEEE Trans. on Circuits and Systems, vol. CAS-33, no. 11, pp. 1147-1149, 1986.
[10]R. Gupta, B. Tutuianu, and L. T. Pileggi, “The elmore delay as a bound for RC trees with generalized input signals,” IEEE Trans. on Computer-Aided Design, vol. 16, pp. 95-104, 1997.
[11] H. Li, Z. Li, and Y. Min, “Delay testing with double observations,” Proceedings of seventh Asian Test Symposium, pp.96-100, 1998.
[12] Pierzynska and Pilarski, “Pitfalls in delay fault testing,” IEEE Trans. on CAD, vol. 16, no. 3, pp.321-329, 1997.
[13]C. J. Lin and S.M. Reddy, “On delay fault testing in logic circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 694-703, issue 5, 1987.
[14]F. Moll and A. Rubio, “Spurious signals in digital CMOS VLSI circuit: a propagation analysis,” IEEE Trans. on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 39, no.10, pp. 749-752, 1992.
[15]C. Wang and K. Roy, “Maximum power estimation for CMOS circuits using deterministic and statistic approaches,” IEEE Trans. on VLSI Systems, vol. 6, no. 1, pp. 134-140, 1996.
[16] B.C. Paul and K, Roy, “Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis,” Proceedings of IEEE International Test Conference, pp. 384-390, 2002.
[17]H. Chang and J.A. Abraham, “CHAN: An efficient critical path analysis algorithm,” Design Automation, with the European Event in ASIC Design. Proceedings, 4th European Conference, pp. 444-448, 1993.
[18] L. Silva, J. Silva, and K. Sakallah, “Realistic delay modeling in satisfiability-based timing analysis,” ISCAS 98, pp.215-218, 1998.
[19] R. Anglada and A. Rubio, “Logic fault model for crosstalk interferences in digital circuits,” International Journal of Electronics, vol. 67, no. 3, pp. 423-425, 1989.
[20] W. Chen, S. Gupta, and M. Breuer, “Test generation for crosstalk-induced delay in integrated circuits,” Proceedings of IEEE International Test Conference, pp. 95-104, 1999.
[21] K. T. Lee, C. Nordquist, and J.A. Abraham, “Automatic test pattern generation for crosstalk glitches in digital circuits,” VLSI Test Symposium. Proceedings, 16th IEEE, pp. 34-39, 1998.
[22] H. Li, Y. Zhang, and X. Li, “Delay test pattern generation considering crosstalk-induced effects,” Proceedings of Asian Test Symposium, pp. 178-183, 2003.
[23] Itazaki, Y. Matsumoto, and K. Kinoshita, “An algorithmic test generation method for crosstalk faults in synchronous sequential circuit,” Proceedings of Sixth Asian Test Symposium, pp.22-27, 1997.
[24]L. Chen, T. Mak, M. Breuer, and S. Gupta, “Crosstalk test generation on pseudo-industrial circuits: a case study,” Proceedings of IEEE International Test Conference, pp.548-57, 2001.
[25]W. Y. Chen, S. K. Gupta, and M. A. Breuer, “Test generation for crosstalk-induced faults: framework and computational results,” Proceedings of Ninth Asian Test Symposium, pp.305-310, 2000.
[26]J. Grodstein, D. Bhavsar, V. Bettada, and R. Davies, “Automatic generation of critical-path tests for a partial-scan microprocessor,” Computer Design Proceedings. 21st International Conference, pp.180-186, 2003.
[27]W. Chen, S. K. Gupta, and M. A. Breuer, “Test generation in VLSI circuits for crosstalk noise,” Proceedings of IEEE International Test Conference, pp. 641-650, 1998.
[28]T. Larrabee, “Test pattern generation using boolean satisfiability,” IEEE Trans. on CAD, vol. 11 no. 1, pp.4-15, 1992.