臺灣博碩士論文加值系統

現今無線傳能技術廣泛的應用於生醫電子及RFID等積體電路應用。一個高電源拒斥調節器為生醫電路與系統所需。高電源拒斥調節可抑制電源雜訊的變化與不同頻率的振幅，不僅降低漣波且提供更穩定的輸出。此外，隨著製程的進步，低功率應用及高效能的積體電路不僅要提供一個穩定電源，在提高效率的部分也將成為設計挑戰。本研究提出一無外部電容之近場無線電源積體電路，除了傳能耦合線圈外，無其它外接原件，利用疊接式低壓線性穩壓器來提高電源拒斥能力來降低輸出漣波，並提升可靠度。測試晶片以台積電0.18μm 1P6M標準製程實現，晶片面積為0.751 0.968 mm2.。量測結果，接收端皆能產生穩定之1.8V直流輸出電壓，以供給1mA負載電流，輸出漣波8.8mV Vpp。

Near-field wireless power transmission is widely used in RFID and biomedical applications. A high PSR regulator is a requirement for biomedical circuits and systems. High PSR regulator can suppress the power supply noise which can have large variations of amplitude and of different frequencies to be able to provide a more stable output and reduced ripple. Moreover, with the advancement of process technologies for low power applications, a reliable and efficient power integrated circuit not only to provide a stable supply but also to maximize efficiency becomes a design challenge. This work presents a near-field wireless power integrated circuit without external capacitors where the only external component is the coupling coil. The output ripple is minimized by utilizing a high PSR low dropout regulator using a cascode structure. The measurement results show that the receiver can generate a stable 1.8V DC output voltage to supply 1mA output current. The output voltage ripple is 8.8mV Vpp. The test chip is implemented by TSMC 0.18μm 1P6M process and the chip area is 0.751 0.968 mm2.

CONTENTS

Acknowledgements i
Abstract (Chinese) iv
Abstract (English) v
Contents vi
Figure Captions viii
Table Captions xii

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 Previous Works at the State-of-the-Art 3
2.1 Introduction to Near-field Wireless Power Transmission 3
2.2 Previous Works on Near-field Wireless Power Receiver Sub-circuits 4
2.2.1 Rectifier 4
2.2.2 Limiter 8
2.2.3 Regulator 9
2.3 Near-field wireless power receiver front-end 16

Chapter 3 Proposed Near-field Wireless Power Integrated Circuit 18
3.1 Active Rectifier with High-speed Comparators 19
3.2 High PSR Low Dropout Regulator Using Cascode Structure 25
3.2.1 Auxiliary Low Dropout Regulator 36
3.2.2 Core Low Dropout Regulator 38
3.3 Differential Charge Pump 40
3.4 Bandgap Voltage Reference with Subtractor 42
3.5 Limiter with Additional Diode-Connected Transistors 44
3.6 Constant Gm Bias Circuit 45

Chapter 4 Circuit Implementation and Simulation Results 48
4.1 Chip Implementation 48
4.1.1 Active Rectifier Layout 49
4.1.2 Low Dropout Regulator and Limiter Layout 50
4.2 Post-simulation Results 57
4.2.1 Function-Verification Simulation 57
4.2.2 Corner Case Simulations 59
4.2.3 Bonding Wire Considerations 67

Chapter 5 Chip Measurement Results 72
5.1 Chip Microphotograph 72
5.2 Test considerations and Measurement Results 73
5.3 Comparison Table 83

Chapter 6 Conclusions and Future Works 85
6.1 Conclusions 85
6.2 Future Works 85

References 86



FIGURE CAPTIONS

Fig 2.1 Block diagram of conventional near-field wireless power circuit 3
Fig 2.2 CMOS full-wave voltage rectifier [8] 4
Fig 2.3 Conventional rectifier circuits. (a) simple diode-connected configuration (b) self-Vth-cancellation (SVC) scheme as an example of static gate biasing [9]-[10] 6
Fig 2.4 Differential-drive CMOS rectifier circuit [11] 7
Fig 2.5 I-V characteristic of diode-connected n-channel MOS transistors [11] 8
Fig 2.6 Limiter circuit [7] 9
Fig 2.7 Conventional low dropout regulator [12] 10
Fig 2.8 PSR boost-technique with subtractor [13] 11
Fig 2.9 Schematic diagram of the technique to enhance PSR over a wide range of frequency [14] 12
Fig 2.10 High PSR LDR architecture [15] 14
Fig 2.11 Schematic diagram of high PSR LDR [15] 15
Fig 2.12 Single branch high efficiency charge pump [15] 15
Fig 2.13 Wireless rechargeable battery block diagram [7] 16
Fig 2.14 Front-end rectification and regulation interface [7] 17

Fig 3.1 Block diagram of the proposed near-field wireless power integrated circuit 18
Fig 3.2 Circuit architecture of the proposed near-field wireless power integrated circuit 19
Fig 3.3 Active rectifier with high-speed comparators and dynamic body biasing [16] 20
Fig 3.4 High speed comparator [17] 21
Fig 3.5 Operation of the active rectifier with high speed comparators 21
Fig 3.6 Input node voltages and dynamic body bias voltages of the active rectifier 22
Fig 3.7 Simplified schematic diagram of active rectifier depicting the current path and power dissipating components when VRF+ - VRF- > VREC [16] 24
Fig 3.8 Efficiency of the active rectifier with high speed comparators 25
Fig 3.9 Proposed high PSR low dropout regulator using cascode structure [13]-[15] 26
Fig 3.10 Small signal model of the proposed LDR (a) auxiliary LDR (b) core LDR 28
Fig 3.11 PSR response of the proposed LDR 28
Fig 3.12 Low dropout regulator loop response analysis model 32
Fig 3.13 Loop response simulation for (a) auxiliary LDR (b) core LDR 32
Fig 3.14 Transient response of the proposed LDR 34
Fig 3.15 Efficiency of the low dropout regulator using cascode structure 35
Fig 3.16 Transient simulation of the proposed LDR for (a) line regulation (b) load regulation 35
Fig 3.17 Auxiliary low dropout regulator [14]-[15] 37
Fig 3.18 Frequency response of the two-stage folded cascode amplifier and with RC filter 37
Fig 3.19 Core low dropout regulator [13] 38
Fig 3.20 Frequency response of the two-stage amplifier and with subtractor 39
Fig 3.21 Differential charge pump circuit [11] 41
Fig 3.22 Transient simulation of the differential charge pump circuit 41
Fig 3.23 Bandgap voltage reference with subtractor [20] 42
Fig 3.24 Temperature variation simulation of the bandgap voltage reference circuit with subtractor 43
Fig 3.25 Transient simulation of the bandgap voltage reference circuit with subtractor 43
Fig 3.26 Limiter with additional diode-connected transistors [21] 45
Fig 3.27 Transient response simulation of the limiter circuit with additional diode-connected transistors 45
Fig 3.28 Constant gm bias circuit 46
Fig 3.29 Transient simulation of the constant gm bias circuit for (a) bias voltages (b) bias currents 47

Fig 4.1 Layout of the proposed near-field wireless power integrated circuit 48
Fig 4.2 Floor plan for layout of the proposed circuit 49
Fig 4.3 Active rectifier layout 50
Fig 4.4 Cascode low dropout regulator and limiter circuit layout 51
Fig 4.5 Limiter circuit layout 51
Fig 4.6 Two-stage folded cascode error amplifier with bias circuit layout 52
Fig 4.7 Low-pass RC filter layout 53
Fig 4.8 Differential charge pump layout 53
Fig 4.9 Two-stage error amplifier layout 54
Fig 4.10 Constant gm bias circuit layout 54
Fig 4.11 Subtractor circuit layout 55
Fig 4.12 Bandgap voltage reference circuit with subtractor layout 56
Fig 4.13 Power MOS devices layout (a) MN (b) MP 56
Fig 4.14 Feedback resistors layout for (a) auxiliary low dropout regulator (b) core low dropout regulator 57
Fig 4.15 Transient post-layout simulation of the proposed near-field wireless power integrated circuit (a) node voltages (b) magnified signals 58
Fig 4.16 Efficiency of the near-field wireless power integrated circuit 59
Fig 4.17 Post-layout AC analysis for the PSR of the proposed LDR 60
Fig 4.18 Post-layout transient simulation for the (a) VREC corners (b) magnified VREC signals 60
Fig 4.19 Post-layout transient simulation for the (a) VCP corners (b) magnified VCP signals 61
Fig 4.20 Post-layout transient simulation for the (a) VREF corners (b) magnified VREF signals 62
Fig 4.21 Post-layout transient simulation for the (a) VGN corners (b) magnified VGN signals 63
Fig 4.22 Post-layout transient simulation for the (a) VGP corners (b) magnified VGP signals 64
Fig 4.23 Post-layout transient simulation for the (a) VOUT corners (b) magnified VOUT signals 65
Fig 4.24 Post-layout transient simulation for the (a) LDR line regulation (b) LDR load regulation 67
Fig 4.25 Bonding wire model for the proposed near-field wireless power integrated circuit 68
Fig 4.26 Post-layout AC analysis for the PSR of the proposed LDR with bonding wire model 69
Fig 4.27 Post-layout transient simulation for the input node voltages, VRF+ and VRF-, with bonding wire model 69
Fig 4.28 Post-layout transient simulation with bonding wire model for the (a) VOUTX corners (b) magnified VOUTX signals 70
Fig 5.1 Chip microphotograph of the proposed near-field wireless power integrated circuit 72
Fig 5.2 Test board layout diagram 73
Fig 5.3 Test board with chip and LRES coil 73
Fig 5.4 Function test set-up 74
Fig 5.5 Board set-up for function test 74
Fig 5.6 Function generator configuration for input AC signal 75
Fig 5.7 Function test measured input and output signals 75
Fig 5.8 Function test measured VOUT ripple 75
Fig 5.9 Measured load regulation (a) ripple (b) DC level 76
Fig 5.10 Wireless power transmission test set-up 77
Fig 5.11 Wireless power transmission test (a) transmitter and receiver (b) board set-up 78
Fig 5.12 Measured AC voltages (a) AC voltage on LT (b) AC voltage on LRES 79
Fig 5.13 Measured output voltage, VOUT (a) DC level (b) voltage ripple 80
Fig 5.14 Distance measurement board set-up for wireless power transmission 81
Fig 5.15 Measured input and output signals at 5mm coupling coils distance 81
Fig 5.16 Measured input and output signals at 15mm coupling coils distance 82
Fig 5.17 Measured input and output voltage by different transmitted distance 82


TABLE CAPTIONS

Table I Corner case parameters 59
Table II Corner Case Simulation Summary 66
Table III Performance summary of the proposed circuit 71
Table IV Test instruments 83
Table V Comparison table of this work with others 84

References

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