臺灣博碩士論文加值系統

為了高速之特性，本論文以電流驅動的方式設計此數位類比轉換器(Digital-to-Analog Converter, DAC)，並提出一新型的校正技術，其弁酮停j制降低差動非線性誤差(Differential Nonlinearity, DNL)和總體非線性誤差(Integral Nonlinearity, INL)，進而提高DAC的動態效能，有效加強轉換器之線性度。運用此技術，成它a改善了過去單位電流源(ILSB)需極大面積以降低隨機誤差的缺失，更同時達到高速、高解析和低必v消耗的目標
我們將在此論文中採用TSMC 0.35微米CMOS製程實現一高速的十二位元數位類比轉換器，其最大取樣頻率為400MS/s。其所包含的新型數位校正技術可大幅降低單位電流源面積。另外，即使不需要任何的特別輸出級電路[17][18]，也可於高速操作時保持傑出的動態效能。

We design the Digital-to-Analog Converter (DAC) with Current-Steering architecture to achieve high-speed specification and propose a novel calibration technique in this thesis. The technique could directly suppress the differential nonlinearity (DNL) and integral nonlinearity (INL) and furthermore lift up dynamic performance to increase the linearity of whole DAC effectively. By this technique, we have attained the destination of high speed, high resolution and low power consumption because of successfully improving the drawback caused by requiring large scale area of unit source to drop random error.
The high-speed 12-bit Digital-to-Analog Converter, whose maximum sampling rate is 400MS/s, is implemented in TSMC CMOS process. New digital calibration circuit can keep the performance in an outstanding level even with a dramatically slight unit source area and lack of specific output stage [17][18].

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1

1.2 ORGANIZATION 2
CHAPTER 2 NYQUIST-RATE DAC OVERVIEW 4
2.1 BASIC CONCEPTS AND SPECIFIC PARAMETERS 4
2.1.1 IDEAL DAC 5
2.1.2 STATIC PERFORMANCE 6
2.1.3 DYNAMIC PERFORMANCE 8
2.1.4 SPECTRAL PERFORMANCE 9

2.2 CONSTRUCTION OF DAC 11
2.2.1 RESISTOR-STRING D/A CONVERTER 11
2.2.2 BINARY WEIGHTED ARCHITECTURE 12
2.2.3 THERMOMETER-CODED CURRENT-STEERING DAC 14
2.2.4 SEGMENTED CURRENT-STEERING DAC 15
CHAPTER 3 ANALYSIS AND DESIGN OF PRIMARY DAC BODY 17
3.1 STATIC ERROR 18
3.1.1 SYSTEMATIC ERROR 18
3.1.2 RANDOM ERROR 21

3.2 DYNAMIC ERROR 22

3.3 DESIGN OF CURRENT CELL AND ARRANGING METHOD 24
3.3.1 LIMITATION DUE TO OUTPUT IMPEDANCE 24
3.3.2 MINIMUM REQUIRED AREA OF UNIT CURRENT SOURCE 27
3.3.3 CHOICE OF BIT NUMBER FOR MSB, ULSB AND LLSB 32

3.4 FUNDAMENTAL BUILDING BLOCKS OF PRIMARY BODY 35
3.4.1 BINARY-TO-THERMOMETER DECODER 37
3.4.2 HIGH-SPEED LOW-CROSSING-POINT LATCH 38
3.4.3 BIASING CIRCUITRY 40
CHAPTER 4 CALIBRATION AND MSB ARCHITECTURE 42
4.1 INTRODUCTION AND DESCRIPTION 43
4.1.1 PROPOSED CURRENT MEMORY AND CURRENT RECTIFIER 43
4.1.2 MSB AND CALIBRATION STRUCTURE 45
4.1.3 ANALYSIS OF TWO CALIBRATION DACS 50

4.2 ELEMENT BLOCK OF CALIBRATION 55
4.2.1 1-BIT ADC 56
4.2.2 CONTROLLER 56
4.2.3 POSTPONEMENT EXECUTOR 58
CHAPTER 5 LAYOUT CONSIDERATIONS 60
5.1 LAYOUT 61

5.2 SWITCHING SCHEME 62
CHAPTER 6 SIMULATION AND EXPERIMENTAL RESULTS 66
6.1 STATIC PERFORMANCE 66

6.2 DYNAMIC PERFORMANCE 67

6.3 TESTING CONFIGURATION 70
6.3.1 POWER SUPPLY 71

6.4 EXPERIMENTAL RESULTS 72
CHAPTER 7 CONCLUSION 75
APPENDIX A 76
APPENDIX B 79
APPENDIX C 81
BIBLIOGRAPHY 82

[1]B. Razavi, “Principles of Data Conversion Design,” New York: IEEE Press, 1995.
[2]D. Wouter J. Groeneveld, Hans J. Schouwenaars, Hank Termeer, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters” ISSCC Dig. Tech. papers pp.22-23, February 1989.
[3]Van den Bosch, Mare A. F. Borremans, Michel S. J. Steyaert, Willy Sansen, “A 10-bit 1GSample/s Nyquist Current-Steering CMOS D/A Converter” IEEE Journal of Solid-State Circuits, vol.36, NO. 3, MARCH 2001.
[4]Chi-Hung Lin, Klaas Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, December 1998.
[5]Geourgi I. Radulov, Patrick J. Quinn, Hans Hegt, and Arthur van Roermund, “An on-chip Self-Calibration Method for Current Mismatch in D/A Converters” Proceedings of ESSCIRC, Grenoble France, 2005.
[6]Mika P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC” IEEE JSSCC, vol.36, NO.7, July 200.
[7]Byung-moo Min and Soo-Won Kim, “High Performance CMOS Current Comparator using Resistive Feedback network” ELETRONICS LETTERS vol.34, NO.22, 29th Oct. 1998.
[8]M.J.M, Pelgrom, et al, “Matching properties of MOS Transistors” IEEE J. Solid-State Circuits, vol.24, pp. 1433-1439, Oct. 1989.
[9]A. Van den Bosch, M. Steyaert and Sansen,“An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters” ISCAS 2000, IEEE International Symposium Circuits and Systems, pp. 105-108.
[10]Kuo-Hsing Cheng, C. C. Chen, and P.Y. Li, “A High Accurate and High Output Impedance Current Mirror” in Proc. WSEAS Conf. CSCC, 2002, pp.41-43.
[11]J. Jacob Wikner and Nianxiong Tan, “Modeling of CMOS Digital-to-Analog Converters for Telecommunication,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, No. 5, May. 1999.
[12]Yonghua Cong and Randall L. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, No. 7, July. 2000.
[13]G. Van Der Pla, J. Vandenbussche, W.Sansen, M.Steyaert and G. Gielen, “A 14-bit Intrinsic Accuracy Random Walk CMOS DAC,” IEEE Journal Solid-State Circuits, vol. 34, pp. 1708-1717, Dec. 1999.
[14]K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, A. van Roermund, “ A 12b 500MS/s with >70db SFDR up to 120MHz in CMOS,” ISSCC Dig. Tech. Papers, pp. 116-117, Feb. 2005.
[15]Kevin O’Sullivan, Chris Gorman and Vincent Callaghan, “A 12-bit 320-MSamples/s Current-Steering CMOS D/A Converter in 0.44 ,” IEEE Journal of Solid-State Circuits, vol. 39, No. 7, July. 2004.
[16]Jose Bastos, M. Marques, Michel S. J. Steyaert and Willy Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 3, No. 12, Dec. 1998.
[17]Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers and Steven F. Gilling, “A 14-b 100-MS/s CMOS DAC Designed for Spectral Performance,” IEEE Journal of Solid-State Circuits, vol. 34, No. 12, Dec. 1999.
[18]Alex R. Bugeja, Bang-Sup Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000.
[19]Yonghua Cong, Randall L. Geiger, “A 1.5-V 14-Bit 100-MS/s Self-Calibrated DAC,” IEEE Journal of Solid-State, vol. 38, No.12, Dec. 2003.
[20]Yu-Hong Lin, “A 16-bit, High-Speed DAC with Random Multiple Data-Weighted Averaging Algorithm,” Master dissertation, National Cheng Kung University, Taiwan, 2002.
[21]Behazad Razavi, “Principles of Data Conversion System Design,” NJ Press, 1995.
[22]David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” John Wiley&Sons Inc, 1997.
[23]J. Wikner and Nianxiong Tan, “Influence of Circuit Imperfections on the Performances of DACs.” Internal Report, Linkoping University, Sweden, Aug. 1998.
[24]Mark Burns and Gordon W.Roberts, “An Introduction to Mixed-Signal IC Test and Measurements” OXFORD UNIVERSITY PRESS 2001.