臺灣博碩士論文加值系統

本論文提出一個低互擾單電感雙輸出之數位控制式降壓型電壓轉換器。經由調整相序之方式，使此切換式電壓轉換器可以在簡單的架構下於連續電流導通模式具有低互擾之特性，此外本研究亦增加一放電路徑，使降載時的互擾影響降至最低。本論文依電壓模式控制架構進行模型推導，以及分別由時域及頻域角度對系統做穩定度分析，最後以FPGA做數位化控制之驗證。模擬及實驗結果顯示經由換相之控制，單電感雙輸出之任一相負載變動對於另一相造成之互擾可降低為普通電壓模式控制之四分之一以下。

A digitally controlled SIDO buck converter using the Phase Sequence Interchange (PSI) scheme for low cross-regulation is proposed. The voltage-mode SIDO buck converter operated in CCM has simple structure and low cross-regulation characteristic with PSI scheme. In addition, a discharging path is adopted for the load drop condition to further reduce cross-regulation effect. The circuit model derivation for the voltage-mode structure and system stability analyses in both time domain and frequency domain are illustrated in detail. The digital control is implemented and verified by FPGA. Simulation and experimental results show that during one phase transient, the cross-regulation occurs in another phase is reduced to one-fourth of the same magnitude compared to the normal voltage-mode operation of SIDO buck converter.

摘要 I
Abstract II
Acknowledgements III
Contents IV
List of Tables VI
List of Figures VII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 6
Chapter 2 Controls of the SIDO Converter 7
2.1 Structure of SIDO Buck Converters 7
2.2 Operation Principle of SIDO Buck Converters 9
2.3 Control Methods 13
2.3.1 Time-Multiplexing with DCM Operation 13
2.3.2 Non-time-multiplexing with CCM Operation 16
2.3.3 Time-Multiplexing and Non-time-multiplexing with Pseudo-CCM Operation 20
Chapter 3 Modeling and System Analysis of a SIDO Buck DC/DC Converter 23
3.1 Model of Voltage-Mode Controlled SIDO Buck Converter 23
3.1.1 Small-Signal Analysis for a SIDO Buck Converter in CCM mode 23
3.2 Compensator Analysis 36
3.3 Stability Analysis in Frequency and Time Domain Analysis 39
3.3.1 Uncompensated SIDO Buck Converter 39
3.3.2 Compensated SIDO Buck Converter 48
Chapter 4　　Software and Hardware Implementation of Low Cross-regulation Voltage-Mode Control SIDO Buck Converter 57
4.1 Phase Sequence Interchange Scheme 57
4.2 Discharging Path 63
4.3 Main Process of the FPGA-Based Control Algorithm 65
4.3.1 Counter - A Fixed Saw-Tooth 66
4.3.2 Digital PWM Algorithm 67
4.3.3 PSI Start Mechanism 68
4.3.4 Phase Sequence Determination 69
4.3.5 Feedback Signal Select 70
4.3.6 Discharging path 71
4.4 Implementation of the Hardware 73
4.4.1 Power Stage Circuit 75
4.4.2 Analog-to-Digital Converter Circuit 75
4.4.3 Interface Circuit of the FPGA 76
Chapter 5 Simulation and Experimental Results 78
5.1 Simulation Tests 78
5.2 Experimental Results 85
Chapter 6 Conclusions and Future Work 93
6.1 Conclusions 93
6.2 Future Work 93
References 94

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