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During the recent years, the residue number system (RNS) hsa been
receiving considerable interest due to its parallel and fault-tolerant
properties. In this dissertation, a new algorithm for single residue digit
error correction is proposed. This algorithm is fully based on the mixed
radix conversion (MRC) and redundant MR digits can be used to establish a
look-up table to correct single residue digit errors. The necessary and
sufficient conditions for the proposed algorithm are also derived. The
proposed algorithm can be extended to correct errors in the quadratic RNS
(QRNS). It can be shown that single digital pair errors in a QRNS can be
corrected.
Since the scaling and the residue-to-binary conversion can be completed
via the MRC, the relationship between the single error correction (or
detection) and the scaling (or residue-to-binary conversion) is
investigated. Then two operations can be unified in one hardware thereby
reducing the complexity of these implementations, The original scaling
algorithm will reduce the dynamic range. In this dissertation, this
shortcoming can be eliminated by the use of the polarity shift. The
scaling error es is analyzed and found to be limited to the interval of -1
< es < 1. Since the scaling is often required in the computations of
digital signal processing (DSP) which is the primary application of the
RNS, an error correction circuit with scaling (ECCS) or error detection
circuit with scaling (EDCS) will be very efficient in the fault-tolerant
systems for the DSP applications, Two examples for the application of the
proposed ECCS, EDCS or error correction circuit with residue-to-binary
conversion are given :One is the fast Fourier transform (FFT) network and
the other is the infinite impulse response (IIR) filter. Based on the
proposed algorithms, the fault-tolerant FFT networks and IIR filters can
be completed.
Finally, a VLSI layout (using double metal CMOS process and two-phase
nonoverlapping clock strategy) for the proposed single error correction
algorithm is implemented. The moduliset {16,17,19,23,29,31} is used and
the total and dynamic ranges are about 27 and 17 bits, respcctively.
Function and timing verifications are simulated. The chip latency is 8
clock cycles and the throughput is about 10MHz. In this layout
implementation, it can be shown that the proposed algorithm is suitable
for VLSI design.
餘數數字系統(RNS)具有優良的平行處理及容錯特性,近來由於硬體價格的降低，使其
再度受到極大的重視，在本論文中，作者針對單一餘數數字錯誤之更正提出一新型的
演算法，此演算法依據混合基數轉換法(MRC) 之原理，而使冗餘的混合基數數字足以
建立更正表，其所需的充分必要條件皆將於本文中被推導出來。此外，此演算法亦能
推廣到二次餘數數字系統(QRNS)，作者證出在QRNS中，任何單一數字組之錯誤，皆能
被更正。
此演算法最大大的好處，就是能與定比運算(Scalig)結合在同一硬體上，而其定比誤
差經分析結果，是介於－１到１之間，數位訊號處理(DSP)為RNS應用最廣的領域，而
定比運算在DSP 中又常被使用，因之，此演算法將能十分有效地使用於具容錯性質的
DSP 應用中，諸如快速傅立葉轉換(FFT) 及無限脈衝響應濾波器(IIR filter)等。
最後，作者亦完成了此新型演算法的超大型積體電路(VLSI)之佈局，功能及時序的模
擬，並且提出了具有層次性及模組性的設計方法。依此方法，將可發現此演算法相當
適合於VLSI的設計。
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