臺灣博碩士論文加值系統

在本篇論文中﹐我們實現了一個濾波器模組產生器。使用者能夠藉由此產生器﹐自動設計出高速低複雜度的數位有限脈衝響應多速率濾波器。此產生器利用線性相位濾波器的對稱性架構﹐並運用多級多速率IFIR濾波器的方法﹐以達到低複雜度之目的。此外﹐運用polyphase representation將濾波器分解成多個子濾波器。所產生的濾波器﹐利用CSD乘法器、transposed direct式架構、和CSA以達到高速的要求。為了擁有良好的適應性﹐輸出的程式碼將以可合成的行為階層硬體描述語言撰寫﹐讓合成工具軟體能依據使用者所指定的條件選擇最適合的架構。
最後﹐我們提供了一個用於64-QAM基頻解調器的濾波器設計實例。使用Synopsys的合成工具並採用TSMC 0.25μm製程設計晶片。結果在低複雜度應用方面﹐減少了32%的面積﹐並節省下44%的功率消耗。而對於高速應用方面﹐此晶片能操作在680 MHz。除此之外﹐還有兩個以此模組產生器設計多階多速率濾波器的例子。

A module generator, which can automate the process of designing high-speed low-complexity multirate FIR digital filters, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. The generator is designed for maximum flexibility that the output codes are written in a synthesizable behavioral level hardware description language (HDL), which allows the synthesis tool to select the appropriate architecture from user’s constraints.
Finally, a filter design example for 64-QAM baseband demodulator is given. The chip is deigned with TSMC 0.25um process by using the synthesis tool of Synopsys. The area is reduced by 32 percent and the power dissipation is saved by 44 percent for low-complexity applications. Moreover, for high-speed application, the chip can operate at 680 MHz throughput rate. In addition, results of two multistage multirate examples designed with the module generator are also presented.

Chapter 1 Introduction
1.1 Introduction.........................................................................................1
1.2 Motivation...........................................................................................3
1.3 Thesis Organization ............................................................................4
Chapter 2 FIR Digital Filter Design
2.1 Basic FIR Filter Structures .................................................................6
2.1.1 Direct Form Structure ......................................................................7
2.1.2 Transposed Direct Form Structure...................................................9
2.1.3 Carry Save Addition ......................................................................10
2.1.4 Linear Phase FIR Filters ................................................................12
2.2 Multiplierless Filter Design ..............................................................14
2.2.1 CSD Representation.......................................................................14
2.2.2 CSD Multipliers.............................................................................17
2.3 Pipelining..........................................................................................19
2.4 Sign Extension Elimination ..............................................................21
Chapter 3 Multirate FIR Digital Filter Design
3.1 Basic Multirate Operations ...............................................................24
3.1.1 Decimation.....................................................................................24
3.1.2 Interpolation...................................................................................27
3.2 The Noble Identities .........................................................................30
3.3 The Polyphase Representation..........................................................31
3.3.1 Structures for Decimator and Interpolator .....................................33
3.4 Interpolated FIR Filter Design..........................................................38
3.5 Multistage Multirate Filter Design ...................................................40
Chapter 4 Module Generator Implementation
4.1 System Specifications.......................................................................43
4.2 Multistage Architecture Analysis......................................................45
4.3 Coefficient Calculation .....................................................................47
4.4 Coefficient Optimization ..................................................................47
4.4.1 Scaling Strategy.............................................................................49
4.4.2 Local Search Strategy....................................................................51
4.4.3 Overflow Prevention......................................................................52
4.5 Word Length Estimation...................................................................53
4.6 Hardware Estimation ........................................................................55
4.6.1 Hardware Estimation for Single-Stage Design..............................55
4.6.2 Hardware Estimation for Multistage Design .................................55
4.7 Synthesizable Verilog Code Generation ...........................................56
Chapter 5 Experimental Results
5.1 Lowpass Filter ..................................................................................58
5.2 Interpolator .......................................................................................64
5.3 Decimator .........................................................................................65
Chapter 6 Conclusions
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