臺灣博碩士論文加值系統

近年來通訊網路的資料傳輸速率急速成長，使得背版實體層介面上的電路設計遇到相當大的挑戰。隨著資料速率達到每秒十億位元以上，碼際干擾逐漸成為數位通信上非常重要的一個課題－它限制了有線通訊的傳輸速率以及傳輸距離。

在電路補償通道衰減方面，可以使用數位或類比的等化器。與類比等化相比，數位等化擁有比較精確的表現，但以數位方式實現等化器在高速類比╱數位轉換器的製作上有著很大的瓶頸。數位等化所需的大面積、高功率消耗使純類比的等化器成為一個更有效率的解決方案。

在本論文中，我們設計了一個適用於FR-4 PCB背版連線的四振福調變 (4-PAM)類比通道等化器。此類比等化器使用總和回授濾波器 (sum-feedback filter)，可解決一般前授濾波器(feed-forward filter)常見的設計難題。電路實作上使用標準0.18微米互補金氧半導體製程，所設計的類比等化器可以成功地回復經由40英吋FR-4 PCB背版傳輸之每秒140億位元的隨機信號；在1.8伏電源供應下，功率消耗為121毫瓦。此電路的晶片面積為1.285× 0.98毫米平方。

The exploring increasing of data rate has created a major challenge for electronic circuits used at the interface of the backplane physical layer links. As the data rate increases above Gb/s, intersymbol interference (ISI) becomes an essential issue in digital communications, limiting the achievable transmission speed and distance over channels.

As to electronic compensation for the channel loss, digital or analog equalizers can be used. Digital (DSP based) equalization offers more accurate and higher performance comparing with analog counterpart. But the design of digital equalization has a bottleneck on the implementation of high-speed ADCs, which need large area and high power consumption. Consequently, pure analog equalizer is a more efficient solution.

In this thesis, a 4-PAM (pulse amplitude modulation) adaptive analog equalizer is proposed to compensate the FR-4 PCB backplane interconnections by using a sum-feedback filter (SFF), relaxing the design requirement of the conventional analog feed-forward equalizers (FFE). 4-PAM is also adopted to increase the transmission data rate over bandwidth-limited channel. Fabricated in a standard 0.18-μm CMOS technology, the analog equalizer can successfully recover the 14 Gb/s random data transmitted over 40-inch copper channels while dissipating 121 mW from a 1.8-V power supply. The die size is 1.285 × 0.98 mm2.

Chapter 1　Introduction 1
1.1　Motivation and Research Goals 1
1.2　Thesis Overview 2

Chapter 2　Backplane Environment and Basic Concepts 5
2.1　Backplane Environment 5
2.1.1　Printed Circuit Board (PCB) 5
2.1.2　FR-4 Substrates 6
2.2　Basic Concepts 8
2.2.1　Random Binary Sequence 8
2.2.2　Eye Diagram 9
2.2.3　Bit Error Rate (BER) 12
2.2.4　Bit Error Rate for M-PAM Signal 14

Chapter 3　System Architecture of Analog Equalizer for Backplane Communication 17
3.1　Introduction 17
3.1.1　Equalizer 17
3.1.2　Analog Equalizer 19
3.2　Architecture of Analog Equalizer 19
3.2.1　Conventional Analog Filter Equalizer 20
3.2.2　Analog FIR Filter Equalizer 22
3.3　Channel Model 23

3.4　Architecture of Sum-feedback Filter 24
3.4.1　Design Issues of Analog Equalizer 24
3.4.2　Advantages of Sum-Feedback Filter 25

Chapter 4　Implementation of Analog Equalizer for Backplane Interconnection 29
4.1　Architecture 29
4.1.1　Block Diagram 29
4.1.2　Behavioral Simulation 30
4.2　Sum-feedback Filter 31
4.3　2-bit Slicer and DA Converter 33
4.4　Adaptive Control Loop 34
4.5　Transistor-Level Simulation of Analog Equalizer 35

Chapter 5　Experimental Results of Proposed Analog Equalizer 37
5.1　Chip Die Photo 37
5.1.1　Die Photo 37
5.1.2　4-PAM Signal Generation 38
5.2　Testing Strategy 38
5.2.1　Testing Strategy for the Chip fabricated in 0.18-μm 38
5.2.2　Testing Strategy for the Chip fabricated in 0.13-μm 40
5.3　Measurement Results 41
5.3.1　Measurement Results for the Chip fabricated in 0.18-μm 41
5.3.2　Measurement Results for the Chip fabricated in 0.13-μm 42

Chapter 6　Conclusions and Further Discussions 45
6.1　Conclusions 45
6.2　Further Discussions 46
6.2.1　Comparator mismatch 46

Bibliography 49

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