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研究生:蔡仁杰
論文名稱:具自動負載偵測與擾動式導通時間技術來達到高效率與低諧波失真的功率因素校正控制器
論文名稱(外文):High Efficiency and Low Total Harmonic Distortion Power Factor Correction Controllers with Automatic Loading Detection and Perturbation On-time Techniques
指導教授:陳科宏陳科宏引用關係
學位類別:博士
校院名稱:國立交通大學
系所名稱:電控工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:94
中文關鍵詞:擾動的導通時間控制總諧波失真功率因素校正交錯式功率因素校正
外文關鍵詞:Perturbation on-time control (POT)total harmonic distortion (THD)power factor correction (PFC)interleaving power factor correction
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在現今的綠能源與大電力系統中,功率因素校正控制器變的越來越受重視。主要原因是功率因素校正控制器可以顯著的降低系統總諧波失真並且提高系統使用效率。而功率因素校正控制器主要都利用在離線式的電源供應器,其用來調節輸入電流,使輸入電流與電壓呈現一個同相位的波形。利用此特性,可以使交流訊號源充分的增加與提供實功率到系統上面。
在此篇論文中,首先提出了一個擾動式導通時間的技術,此技術主要應用在功率因素校正控制器上,此技術不但可以有效的抑制總諧波失真的問題,並且可以有效的改善功率因素。除此之外,更提出了一個可以遮蔽時間的控制方法,此方法主要是用來調整控制開關的最小關閉時間。此遮蔽時間的控制方法可以有效的改善效率,即使在一個很低的交流輸入電壓。此全積體化的功率因素校正控制器已使用台灣積體電路製造股份有限公司點五微米的800伏特超高壓製程實現。此晶片可以達到僅6%的低總諧波失真,與高達99%的功率因素,並且在輸出功率90瓦特的時候可以達到95%的高轉換效率。
第二,介紹了一個可以自動負載偵測的技術,此技術主要應用在交錯式功率因素校正器上,此方法可以使應用在寬輸出功率範圍的交錯式功率因素校正器達到一個高效率的輸出。交錯式功率因素校正器的主要優點不但有著較小的輸出漣波,並且有著較小的輸入輸出濾波器,在加上了自動負載偵測的技術之後,可以在較低輸出負載時自動降低切換損失來達到改善效率的功能,因此可以廣泛的應用在手持電子的變壓器上。此自動負載偵測的技術可以自動偵測輸入電壓與導通時間來計算出輸出功率的使用狀態來降低切換損失,利用此機制,可以在較低輸出負載的時候完全關閉附屬通道來達到提升效率的功能。因此臨界導通模式控制可以在較低與較高的輸出負載中同時提供高輸出功率與高轉換效率。此測試電路已經在台灣積體電路製造股份有限公司點五微米的800伏特超高壓製程被製造,此全積體化的交錯式功率因素校正器可以提供一個180瓦特之高功率輸出,並且在極寬的負載變動範圍中皆可以達到92%以上的轉換效率。

The power factor correction (PFC) controller is more popular in today’s green power mainstream for improving power utilization efficiency. The power factor correction shapes the input current of off-line power supplies to increase the real power available from the AC source.
First, the proposed perturbation on-time (POT) technique suppresses total harmonic distortion (THD) and thus improves the power factor (PF) in the power factor correction (PFC) controller. Besides, the adaptive controls of the minimum off-time by the proposed inhibit time (IT) control can improve efficiency even at low AC input voltage. Therefore, highly integrated PFC converter fabricated in the TSMC 800-V ultrahigh voltage process can achieve low THD of 6%, high power factor (PF) of 99%, and high efficiency of 95% at the output power of 90W.
Second, the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving PFC over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Specification of the Harmonic Limitation 4
1.3 Motivation 6
1.4 Thesis Organization 7
Chapter 2 Fundamental of the PFC 8
2.1 Definition of THD and PF 8
2.1.1 THD 8
2.1.2 PF 10
2.2 Properties of the Ideal Rectifier 11
2.3 Realization of a Near-Ideal Rectifier 15
2.4 Classification 17
2.5 BCM Control of the Current Waveform 18
2.6 The Waveform of Interleaving BCM Boost PFC Controller 22
Chapter 3 Perturbation On-time (POT) Technique in PFC Controller for Low Total Harmonic Distortion and High Power Factor 25
3.1 Introduction 25
3.2 The Design Concept Based on the PF and the THD 28
3.3 Proposed PFC Controller with the POT and the IT Technique 33
3.3.1 The POT technique 33
3.3.2 The inhibit time (IT) control 40
3.3.3 The system stability 40
3.4 Circuit Implementation 41
3.4.1 The POT technique circuit 41
3.4.2 The inhibit time (IT) control circuit 44
3.4.3 The NNV-ZCD circuit 45
3.4.4 The UHV start-up circuit 49
3.4.5 The spike-free circuit 50
3.4.6 Reference Voltage 52
3.4.7 The Driver circuit 53
3.5 Experiment Results 55
3.6 Conclusion 67
Chapter 4 Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving PFC Over a Wide Output Power of 180W 68
4.1 Introduction 68
4.2 Interleaving PFC Controller with the ALD Technique 71
4.3 Circuit Implementation 76
4.3.1 The peak detection circuit 76
4.3.2 ALD circuit 77
4.4 Experiment Results 79
4.5 Conclusion 83
Chapter 5 Conclusions and Future Works 84
5.1 Conclusions 84
5.2 Future Works 85
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