臺灣博碩士論文加值系統

本論文提出一個應用於H.264/AVC之畫質可調式分數型移動估測矽智財之設計及實作。主要的設計概念構築於藉由對相同硬體進行不同的設定，可使之支援於多種解析度與編碼品質之要求。為此，在本論文中提出一個三模式分數型移動估測演算法，依所需運算量由多至少分別為”完整模式”、”精簡模式”及”單一模式”。其中單一模式具有最小的運算量，適合可攜式裝置之使用；完整模式則適用於高畫質要求之視訊，其平均PSNR失真為0.007dB，但在某些狀況中，具有超越JM所採用之演算法的效能；而精簡模式則可達到HD720影像之編碼。另外，為了再加強對可攜式裝置之支援性，在本論文中更提出了一套大幅降低硬體成本之設計，稱之為輕量化畫質可調式分數型移動估測設計(Light QS-FME)。論文中所提出之畫質可調式分數型移動估測及輕量化型之二種設計根據CCU 0.13um CMOS製程，分別需要180232 gates及 59394 gates，以及分別對應於搜尋範圍[-16, +15], [-40, +39] 之記憶體的大小分別為27.264 Kbits / 87.936 Kbits。所提出之二項設計其最高工作頻率均為150 MHz，可應用於QCIF、CIF、SDTV (720 x 480)及HDTV (1280 x 720)之即時編碼系統。

This thesis presents a quality scalable fractional motion estimation (QS-FME) IP design for H.264/AVC video coding application. The proposed design is based on the algorithm of QS-FME which supports 3 modes, including full mode, reduced mode and single mode, with different computational complexity. Compare to full mode, the single mode can reduce 90% computation complexity and suite for portable devices. Full mode can achieve average PSNR drop in 0.007 dB. In some cases, the full mode even has better compression quality than the algorithm in JM9.3. About the reduced mode, it can achieve real-time encoding of HD720 sequences. In order to enhance the application of portable devices, we also developed a cost-down customized QS-FME, named Light QS-FME. According to CCU 0.13um CMOS technology, the proposed design of QS-FME and Light QS-FME costs 180232 and 59394 gates as well as 27.264 Kbits/87.936 Kbits local memory for search ranges [-16, +15] and [-40, +39] respectively. The maximum operation frequencies are all 150 MHz and can achieve real-time motion estimation on QCIF, CIF, SDTV (720 x 480), and HD720 (1280 x 720) video sequences.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Thesis Organization 4
Chapter 2 Previous Works 5
2.1 Overview of Fractional Motion Estimation 5
2.2 The Relationship of Integer Motion Estimation and Fractional Motion Estimation 8
2.2.1 Algorithm of Quality Scalable Integer Motion Estimation 8
2.2.2 Architecture of Quality Scalable Integer Motion Estimation 10
2.3 The Existing Architectures of Fractional Motion Estimation 11
Chapter 3 Proposed FME Algorithm and Software implementation 19
3.1 System Analysis 19
3.2 Algorithm of Quality Scalable Fractional Motion Estimation 20
3.3 Software Implementation and Simulation Results 29
Chapter 4 Proposed FME Architectures 34
4.1 Analysis of Hardware Requirement 34
4.2 Architecture of Quality Scalable Fractional Motion Estimation 35
4.3 Architecture of Light QS Fractional Motion Estimation 53
Chapter 5 Design Implementation, Integration, and Verification 59
5.1 Design Implementation 59
5.2 Design Integration 62
5.3 Design Verification 63
5.3.1 ME RTL-level Verification 64
5.3.2 ME Gate-level Verification 66
5.4 ME Application and System Integration 67
5.4.1 ME/Intra Accelerator IP with ME IP 67
5.4.2 H.264 / AVC Video Encoder ASIC IP 68
5.5 System Verification 69
5.5.1 H.264 Encoder System Hardware-Software Co-Simulation Verification 69
5.5.2 H.264 Encoder System FPGA Verification 70
Chapter 6 Performance Comparison 75
Chapter 7 Conclusion 77
References 78
Appendix 80
I. FME Port List and Communication Protocol 80
II. ME/Intra Accelerator Port List and Communication Protocol 81
III. Conformance testing sequences 82
Paper Publication 86
Patent Application 87

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