臺灣博碩士論文加值系統

Recently, the silicon technology of high-density multi-level cell reduced the flash memory production cost. However, it leads the reliability decreasing problem due to the lower endurance and higher disturb failure rate. The parity also called as Error correction code (ECC) is used to correct the error bit when the read data from the flash memory was detected error. The ECC and the data information are stored in the spare area which is a small size of space. The parity code is the most important for the user data, if the bit error had been occurred from the spare area, the spare area ECC which is used to correct the spare area can’t correct the parity code, the error data will causes the page error totally. We use the hybrid SLC/MLC Architecture to place the ECC code in SLC to avoid the information which was stored in spare area to be corrupted. Otherwise, when The ECC is no longer stored in a fixed size, the powerful correction code can be allocated, because the code length is not limited by spare area size anymore, the stronger ECC will directly enhance the reliability of the flash memory.

Recently, the silicon technology of high-density multi-level cell reduced the flash memory production cost. However, it leads the reliability decreasing problem due to the lower endurance and higher disturb failure rate. The parity also called as Error correction code (ECC) is used to correct the error bit when the read data from the flash memory was detected error. The ECC and the data information are stored in the spare area which is a small size of space. The parity code is the most important for the user data, if the bit error had been occurred from the spare area, the spare area ECC which is used to correct the spare area can’t correct the parity code, the error data will causes the page error totally. We use the hybrid SLC/MLC Architecture to place the ECC code in SLC to avoid the information which was stored in spare area to be corrupted. Otherwise, when The ECC is no longer stored in a fixed size, the powerful correction code can be allocated, because the code length is not limited by spare area size anymore, the stronger ECC will directly enhance the reliability of the flash memory.

1 Introduction 5
2 Preliminary 9
2.1 Error Correction Code (ECC)
2.2 Reliability Issue of MLC
2.3 Hybrid Storage Device
3 Adaptive ECC Scheme
3.1 Overview .
3.2 Management of Mapping Information
3.3 Buffer Area and ECC Area
3.4 Upgrade of Error Correction Capability
3.5 Garbage Collection and Wear Leveling
4 Implementation Remark 25
4.1 Parallel Access ECC and Data
4.2 Power Failure
5 Quantitative Analysis 30
5.1 Impact of ECC Location
5.2 Impact of Different ECC Capability
5.3 Impacts of SLC Size
6 Experimental Results 35
6.1 Experiment Setup
6.2 Extended Lifetime of MLC Storage System
6.3 Management Overhead and Wear Leveling
7 Related Work
8 Conclusion and Future Work

1] Flash File System. Technical report, Intel Corporation.
[2] Flash-memory Translation Layer for NAND flash (NFTL). Technical report, M-Systems, 1998.
[3] TN-29-64:Software Device Drivers for Small Page Micron@NAND Flash Memory. Technical report, Micron Technology, 2011.
[4] Yu Cai, Erich F. Haratsch, and Ken Mai. Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. In IEEE DATE, 2012.
[5] Li-Pin Chang. A Hybrid Approach to NAND-Flash-Based Solid-State Disks. IEEE Transactions on Computers, 59:1337 – 1349, Oct 2010.
[6] Li-Pin Chang and Chun-Da Du. Design and Implementation of an Efficient Wear-Leveling Algorithm for Solid-State-Disk micro-Controllers. ACM Transactions on Design Automation for Electronic Systems, 15:1 – 36, Dec 2009.
[7] Li-Pin Chang and Tei-Wei Kuo. An adaptive striping architecture for flash memory storage systems of embedded systems. In Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’02), RTAS ’02, pages 187–196, 2002.
[8] Yuan-Hao Chang and Tei-Wei Kuo. A Commitment-based Management Strategy for the Performance and Reliability Enhancement of Flash-memory Storage Systems. In ACM/IEEE Design Automation Conference (DAC), July 2009.
[9] Scott Chen. What Types of ECC Should Be Used on Flash Memory? Technical report, SPANSION, Nov 2007.
[10] Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, and Cheng-Wen Wu. An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. In VLSI Test Symposium, 2009. VTS ’09. 27th IEEE, pages 53–58, May 2009.
44[11] Jen-Wei Hsieh, Tei-Wei Kuo, Po-Liang Wu, and Yu-Chung Huang. Energy Efficient and Performance-Enhanced Disks Using Flash-Memory Cache. In Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2007), pages 334–339, August 2007.
[12] Ashish Jagmohan, Michele Franceschini, Luis A. Lastras-Montano, and John Karidis. Adaptive Endurance Coding for NAND Flash. In GLOBECOM Workshops (GC Wkshps), 2010 IEEE, pages 1841–1845, Dec 2010.
[13] DAWOON JUNG, JEONG-UK KANG, HEESEUNG JO, JIN-SOO KIM,
and JOONWON LEE. Superblock FTL: A Superblock-Based Flash Translation Layer with a Hybrid Address Translation Scheme. In ACM Transactionson Embedded Computing Systems,, Vol. 9, No. 4, Article 40, March 2010.
[14] Jeong-Uk Kang, Jin-Soo Kim, Chanik Park andHyoungjun Park, and Joon-won Lee. A multi-channel architecture for high-performance nand flash-based storage system. Journal of Systems Architecture, 53:644–58, Sep 2007.
[15] Taeho Kgil, David Roberts, and Trevor Mudge. Improving NAND Flash Based Disk Caches. In IEEE ISCA, 2008.
[16] Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon
Park, and Ha-Joo Song. A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. In ACM Transactions on Embedded Computing Systems, Vol. 6, No. 3, Article 18, July 2007.
[17] Y. Lee, S. Jung, and Y. H. Song. FRA: A flash-aware redundancy array of flash storage devices. In IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, pages 163–171, Oct 2009.
[18] Rino Micheloni, Luca Crippa, and Alessia Marelli. Inside NAND Flash Memories. Springer Science+Business Media, 2010.
[19] MICRON. TN-29-25: Improving Performance Using Two-Plane Commands Introduction. Technical report, MICRON, 2007.
[20] Youngwoo Park, Seung-Ho Lim, Chul Lee, and Kyu Ho Park. A Scalable Flash Memory File System for the Hybrid Architecture of Phase-change RAM and NAND Flash. In ACM SAC, March 2008.
[21] Samsung. WinCE 6.0 MLC NAND Solution (PocketMory) Porting Guide . Technical report, Samsung, 2009.
[22] Sandisk. Solid State Drives Data Reliability and Lifetime White Paper . Technical report, Sandisk, 2008.
[23] Chin-Hsien Wu and Tei-Wei Kuo. An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), pages 601–606, November 2006.