臺灣博碩士論文加值系統

現今積體電路技術發展成熟，矽基(Silicon-Based)技術在電子元件微小化過程中，進到奈米尺寸後由於受到製程能力、元件物理的限制，無不思考不同方法，以突破效能無法提昇的困境；其中矽鍺(Silicon Germanium, SiGe)技術利用矽鍺/矽(SiGe/Si)異質介面、晶格不匹配，以及易與主流技術互補式金屬氧化層半導體(CMOS)製程相容的特點。在高頻特性下，比矽晶具有較佳的低雜訊及低功率損耗優點；相較於砷化鎵(GaAs)，具有較優的高集積度、高電子傳導頻率，及製造良率較高的優勢。目前晶片多整合成單晶片系統(SoC)，為了解決各個子電路時脈相位不同的問題，需要鎖相迴路(PLL)來減少相位偏差，使系統的時脈相位一致，減低輸出資料的錯誤。

本論文所提出的寬頻鎖相迴路是用台積電矽鍺0.18微米製程所設計，利用開關切換三顆壓控振盪器，再藉由三倍頻器產生壓控振盪器的三倍頻訊號來涵蓋整個Q頻帶，提供Q頻帶接收機穩定的本地振盪訊號源，此電路將與三倍頻器及Q頻帶接收機整合成一顆完整的IC。

論文的第一部分先介紹寬頻鎖相迴路的幾個基本架構，探討每種架構的優缺點，第二部分則分別介紹所設計鎖相迴路的子電路，第三部分展示模擬結果與量測結果，最後部分則是論文總結，並說明此設計遇到的難題以及未來的改進方向。

Today’s integrated circuit technology is mature. Silicon-Based technology is in the process of miniaturization of electronic components. After entering the nanometer size, due to the limitations of process capability and component physics, all methods are considered to solve the dilemma of upgrading. Among them, Silicon Germanium (SiGe) technology utilizes a SiGe /Si heterointerface, lattice mismatch, and is compatible with mainstream complementary metal oxide semiconductor (CMOS) processes features. For high frequency characteristics, it has better low noise and lower power . Compared with gallium arsenide (GaAs), it has superior high integration, high electron conduction frequency, and high manufacturing yield. Now the chips change to System-on-Chip (SoC). In order to solve the problem of different clock phase of each sub-circuit, a phase-locked loop (PLL) is needed to reduce the phase deviation and make the clock phase of the system coincide and reduce the error of the output data.

In this paper, the proposed wideband phase-locked loop is used by TSMC SiGe 180-nm BiCMOS process design, using the switch to control three voltage-controlled oscillator, and connecting it to the tripler to generate the signal . It covers the entire Q-band, to provide Q-band receiver a stable local oscillator signal source.

The first part of this paper will introduce the basic structure of wideband phase-locked loop, to explore the advantages and disadvantages of each architecture. The second part is the design of the PLL circuit. The third part shows the simulation result and measurement result of the circuits mentioned in the second part. The final part is the paper summary, the problems I encountered in this design and the improvement direction to the future.

Contents
摘要 I
Abstract II
Figure Captions V
Table Captions 錯誤! 尚未定義書籤。
第一章 簡介 1
1.1 相關背景與動機 1
1.2 論文概要 2
第二章 寬頻壓控振盪器 3
2.1 開關式電容共振腔 3
2.2 開關式電感共振腔 3
2.3 開關耦合電感共振腔 4
2.4 自我開關電感共振腔 5
第三章 電路設計 6
3.1 VCO電路架構 6
3.1.1電路工作原理 8
3.1.2壓控振盪器原理 8
3.1.3輸出緩衝放大器 9
3.2 電流模式邏輯除頻器(CML)電路架構 11
3.3 可程式除頻器 10
3.3.1 除二/三電路 122
3.3.2 多級除二/三電路 1414
3.3.3 工作原理 15
3.4迴路濾波器 15
3.5環型鎖相迴路 17
3.5.1 環型鎖相迴路設定 17
3.5.2 環型震盪器 20
3.5.3 鎖相迴路雜訊分析 22
第四章 量測結果 24
4.1寬頻壓控振盪器 2424
4.2電流模式邏輯除頻器(CML) 2426
4.3可程式除頻器 28
4.4環型鎖相迴路 30
4.5對於低噪聲放大器的封裝量測 32
4.5.1 OMMIC 2~18 GHz LNA 32
4.5.2 CMD229 by Custom MMIC 5~11 GHz LNA 34
第五章 結論 37
5.1 論文總結 37
5.2 未來展望 37
參考文獻 38

 

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