臺灣博碩士論文加值系統

本論文主要目的在建立一個簡易且經過驗證的動態多重派發處理器架構，用於缺乏編譯器技術的研究人員或機構，進行處理器架構與其周邊加速電路的開發。為了利於開發人員使用，將詳細說明進行設計時會遇到的問題，以及如何去進行初步的驗證。

多重派發是指在一顆處理器核心實行了指令級並行運算(Instruction-level parallelism)。這種技術能夠在相同的CPU頻率實現更高的指令吞吐率，進而加速程式執行速度。

在架構設計方面我們採用RUU(Register Update Unit)模型進行設計，其架構在暫存器重命名(Register Renaming)有著較低複雜度的優點，利於修改。同時在解決資料危障(Data Hazard)方面，我們也只以暫存器重命名來進行解決。在執行階段，我們使用執行槽的概念，來避免結構上的危障，同時具有亂序執行(out-of-order execution)的能力。但由於管線的深度增加，須另外考慮支援分支預測(Branch predictor)的架構，來降低分支的懲罰。

驗證方面，由於暫存器重命名演算法是動態地進行，設計人員無法有效測出設計中出現的錯誤。因此我們同時建立了一個測試環境，使得驗證方面可以檢查每一條指令的執行結果。而本架構較傳統的5-Stage Pipeline架構增加了約4.6倍的面積下，效能約有一倍的提升，在時脈方面以FPGA評估也有約增加30Mhz。

This thesis aimed at that how to build a simple and verified processor architecture with dynamic multiple issue. The proposed method is to develop a suitable processor architecture and its surrounding acceleration circuits for the researchers with lack of compiler technology. In order to reduce the use of difficulty, we will detail the description of design problems.

Multiple issue is a processor core has ILP (Instruction-level parallelism) computing. This technology can achieve higher instruction throughput at the same CPU frequency, thus accelerating program execution speed.

In the architecture of the design, we use RUU (Register Update Unit) model. This architecture has lower complexity in register renaming. At data hazard, we only use register renaming to resolve this problem. In the execution stage, we use the execution slot to avoid structure hazard. It also has the ability of out-of-order execution. However, because of the increasing depth of the pipeline, we should add the branch prediction circuit to reduce the punishment of the branch.

The renaming algorithm makes verification difficult, so we also setup a test environment where the verification can reach instruction level. While compared to the traditional 5-Stage Pipeline architecture, the area of the proposed architecture increased 4.6 times and the performance is faster (about double speed). The clock on FPGA also increased 30Mhz.

摘要 ii
ABSTRACT iii
誌謝 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1. 研究動機 1
1.2. 研究目標 2
1.3. 論文架構 2
第二章 指令集介紹 3
2.1. MIPS32指令集 3
2.1.1. 指令格式 4
2.1.2. 指令類型 5
2.1.3. 分支延遲槽 6
第三章 超純量背景知識 8
3.1. 多重派發 8
3.1.1. 靜態多重派發 9
3.1.2. 動態多重派發 10
3.2. 資料危障 11
3.3. 亂序執行 12
3.4. 暫存器重命名 13
第四章 架構設計與分析 15
4.1. Overview 15
4.2. Instruction Fetch Stage 17
4.2.1. Branch predictor 17
4.2.2. 指令對齊問題 20
4.2.3. Instruction Fetch 設計 22
4.3. Instruction Decode Stage 23
4.4. Register Rename Stage 26
4.5. Execute Slot 31
4.5.1. Wake List 32
4.5.2. Instruction FIFO 32
4.5.3. Register File 36
4.5.4. Execute Stage 36
4.5.5. Reorder Buffer 37
4.5.6. Commit Stage 37
4.5.7. 執行槽總結 38
第五章 驗證與效能評估 39
5.1. SystemVerilog驗證環境 39
5.2. 效能比較 42
5.3. 硬體比較 45
第六章 結論與未來方向 47
6.1. 結論 47
6.2. 未來工作 48
參考文獻 49

[1] D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 4/e, 2008.
[2] Iro Pantazi-Mytarelli , "The history and use of pipelining computer architecture: MIPS pipelining implementation," in Systems, Applications and Technology Conference (LISAT), IEEE Long Island, 2013.
[3] M. N. Thakare and G. D. Korde, "Design and simulation of 32-Bit RISC architecture based on MIPS using VHDL," in Advanced Computing and Communication Systems, International Conference, 2015.
[4] D. Wang, "The design of five-stage pipeline CPU based on MIPS," in Electrical and Control Engineering (ICECE), International Conference, 2011.
[5] Aisar Labibi Romas, Siti Intan P and Trio Adiono, "A pipelined double-issue MIPS based processor architecture," in Intelligent Signal Processing and Communication Systems, ISPACS International Symposium, 2009.
[6] 周育樑, “支援超純量之ARM9指令集的雙核心架構,” 國立中山大學電機工程學系研究所, 2005.
[7] 賴鈺仁, “以單指令派發亂序執行之指令管道設計適用於嵌入式系統之超純量雙核心架構,” 國立中山大學電機工程學系研究所, 2009.
[8] 林璟汶, “符合電子系統層級設計概念之可參數化超純量亂序執行微處理器設計、分析與實現,” 國立成功大學電腦與通信工程研究所, 2008.
[9] MIPS Technologies, Inc., MIPS32™ Architecture For Programmers Volume I: Introduction to the MIPS32™ Architecture, 2001.
[10] MIPS Technologies, Inc., MIPS32™ Architecture For Programmers Volume II: The MIPS32™ Instruction Set, 2001.
[11] D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach, 5th Ed..