臺灣博碩士論文加值系統

有線傳輸網路上資料量的指數性高速擴張振興起了具高速傳輸性的光纖和電子元件系統的發展。現今的光纖通訊主流乃建立在同歩光纖網絡標準的平台上。透過此系統的應用,光訊資料能夠在不同長度的光纖中完成傳送。在系統傳輸的接收端因為不同長度光纖及相異的傳送路徑會導致訊號大小不一的損耗。如何保持相同大小的訊號以利後端電子介面的接收,例如時脈恢復及再生電路。對於一類比前端電路而言,這是一個關鍵的需求。
極限放大器和自動增益控制電路是兩種常應用來克服接收能量的變動進而保持訊號振幅固定的電路。然而自動增益控制電路需要更長的反應時間及更複雜的類比電路架構,和需要更大的晶片面積來實現。綜合多種考量,極限放大器是較適用於高速的應用。因此,此論文的研究乃集中於極限放大器的設計與實現。

The exponential growth of data in telecommunication networks has rekindled interest in high-speed optical and electric device and systems. The majority of the backbone optical communication systems are based on the SONET standard. In this system, optical data can be transmitted via differential lengths of fiber. At the receiving end, these differential transmission paths result in a large attenuation range of optical signal. How to maintain a constant magnitude for the succeeding electrical interfaces, namely, timing recovery and data regeneration, is the key requirement for analog frond-end of the receiver.
Limiting and automatic gain control (AGC) amplifiers are the two commonly employed measures to keep the signal magnitude constant against the receiving power variation. However, AGC amplifiers require longer settling time and more complicated analog components, and larger chip size than an open-loop type limiter. For this reason, this work will focus on the design and implementation of limiting amplifiers.

Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 2
Reference 4
Chapter 2. Background and Design Issues 5
2.1 Background 5
2.1.1 CMOS Technology 5
2.1.1-1 Speed 6
2.1.1-2 Supply Voltage 8
2.1.1-3 Power 9
2.1.1-4 Noise 10
2.1.2 Optical Communications 11
2.1.2-1 NRZ & RZ Data 12
2.1.2-2 8B/10B Coding 13
2.1.2-3 Impact of Bandwidth Limitation on Random Data 14
2.1.2-4 Eye Diagrams 15
2.1.2-5 Bit Error Rate 17
2.2 Design Issues 21
2.2.1 Input Capacitance 21
2.2.2 Noise Considerations 21
2.2.3 Bandwidth 22
2.2.4 Gain 22
2.2.5 Offset Voltage 22
2.2.6 AM-PM Conversion 23
2.2.7 Optimum stages number for maximum bandwidth 27
2.2.8 Broadband Techniques 29
2.2.8-1 Passive Inductance 29
2.2.8-2 Active Inductance 30
2.2.8-3 Capacitive degeneration 33
2.2.8-4 Negative capacitive and resistance 35
Reference 37
Chapter 3. A 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors 39
3.1 Introduction 39
3.2 Limiting Amplifier Architecture 40
3.2.1 Architecture 40
3.2.2 Circuit Design 41
3.2.2-1 Gain Stage with Folded Active Inductors 41
3.2.2-2 Offset Canceling Network 47
3.2.2-3 Input-Matching And Output-Buffer Stages 49
3.3 Simulation Results 53
3.3.1 AC-Response and Transient Response 54
3.3.2 Group-Delay 54
3.3.3 Performance summary 56
3.4 Experiment Result 56
3.4.1 AC Response 57
3.4.2 Eye-Diagram 58
3.4.3 Dynamic Range 59
3.4.4 Performance Summary & Comparison 60
3.4.5 Die-Photo and PCB Plan 61
Reference 62
Chapter 4. A CMOS Limiting Amplifier using Local Feed-forward Offset Canceling 63
4.1 Introduction 63
4.2 Limiting Amplifier architecture 64
4.2.1 Architecture 64
4.2.2 Circuit Design 64
4.3 Simulation Results 70
4.3.1 AC and transient Response 71
4.3.2 Eye Diagrams 72
4.3.3 AM PM Conversion 73
4.3.4 Performance Summary 73
4.4 Experiment Results 74
4.4.1 AC Response 74
4.4.2 Transient Response 76
4.4.3 Eye Diagrams 77
4.4.4 Performance Summary and Comparison 79
4.4.5 Die-Photo and PCB-Plan 75
Reference 80
Chapter 5. A 2.5Gb/s CMOS Optical Front End 81
5.1 Introduction 81
5.2 Architecture of the optical front end 81
5.2.1 Inverter TIA 82
5.2.2 Scaled-down LA 83
5.2.3 Output Buffer 91
5.3 Simulation results 93
5.3.1 AC Response 94
5.3.2 Eye Diagrams 96
5.3.3 Performance Summary of Simulation Results 91
5.4 Experiment results 97
5.4.1 AC Response 97
5.4.2 Phase Response 98
5.4.3 Eye Diagrams 99
5.4.4 Performance Summary and Comparison 101
5.4.5 Die-photo and PCB-Plan 102
Reference 103
Chapter 6. Conclusion 104
Appendix 106
A.1 A 2.5Gb/s Optical Front End 106
A.1.1 Circuit Design 106
A.1.2 Experimental Results 109
A.2 A Limiting Amplifier using Passive-Inductance Gain-Peaking 114
A.2.1 Gain stage 114
A.2.2 Offset Cancellation Loop 115
A.2.3 Buffer Stage 116
A.2.4 Experimental Results 118
A.3 A 10Gb/s CMOS Limiting Amplifier 123
A.3.1 Gain stage 123
A.3.2 Offset Cancellation Circuit 127
A.3.3 Simulation Result 128

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