臺灣博碩士論文加值系統

根據半導體技術藍圖指出，快閃記憶體在元件尺寸持續微縮下，要提升元件特性又必須維持其可靠度，兩者之間的取捨為未來研究主要方向。
本論文將利用離子轟擊方式，在穿隧層上作輕微的轟擊處理，來增進電荷捕捉/釋放的效能。經離子物理轟擊後，使的薄膜表面粗糙度上升，伴隨著邊際效應而使得局部電場效應提升電荷捕捉/釋放之效能，以及離子轟擊所造成附加的電荷陷阱(Trap sites)，能有效提升整體電荷陷阱密度。
經由分析之後證實離子轟擊能有效的提升電荷捕捉/釋放的效能，電荷寫入/抹除的速度有明顯的增益，而記憶窗也有拉大的趨勢，換言之，我們在相同的記憶窗寬度之比較下，我們能以較低的操作電壓完成動作，能應用於未來降低元件操作電壓之需求。

According to ITRS roadmap, flash memory have some challenge about shrinkage of device size. However, flash memory must maintain the device reliability and improve the device characteristic. These are the main topics for the future research.
We used ion bombardment method as lightly damage on effective tunneling layer to improve the charge trapping/detrapping efficiency. The surface roughness was increased after ion bombardment and the local electrical field mechanism enhance the charge trapping/detrapping efficiency. Otherwise, ion bombardment method brought about additional trap sites that could improve the density of trap site.
The analysis demonstrated that ion bombardment could improve the charge trapping/detrapping efficiency obviously. The program/erase speed was fast either. The memory window width was extended. In other words, we could make the operation voltage lower in the same width of memory window. This method can be made use of decreasing operation voltage for the future demands.

目 錄
摘要…………………………………………………………………i
Abstract……………………………………………………………ii
目錄…………………………………………………………………iv
圖目錄………………………………………………………………vi
表目錄……………………………………………………………viii
第一章 緒論…………………………………………………………1
1.1 前言…………………………………………………………1
1.2 快閃記憶體技術演進………………………………………7
1.3 電荷寫入與抹除機制探討…………………………………14
1.4 研究動機……………………………………………………18
1.5 論文組織架構………………………………………………19
第二章 離子轟擊對於電荷捕捉/釋放效能探討…………… ……21
2.1 簡介…………………………………………………………21
2.2 實驗方法與製程步驟………………………………………21
2.2.1 實驗步驟…………… …………………………………21
2.2.2 實驗步驟…………………………………………… …22
2.2.2.1 電漿原理簡介 ……………………………………22
2.2.3 實驗步驟…………… …………………………………25
2.2.3.1 HfO2薄膜製備…………………………………… 25
2.2.4實驗步驟…………………………………………………26
2.2.5實驗步驟…………………………………………………27
2.3 結果與討論………………………………………………… 29
第三章 總結…………………………………………………………39
第四章 未來工作……………………………………………………40
參考文獻…………………………………………………………… 41
圖目錄
第一章
圖1 快閃記憶體國際半導體技術藍圖…………………………3
圖1.2 MIMIS元件結構示意圖……..……………………………12
圖1.3 Floating Gate Memory能帶圖………………………… 12
圖1.4 改變閘極造成浮動式閘極電荷寫入/抹除………………13
圖1.5 FN穿隧機制……………………………………………… 15
圖1.6 FN 寫入示意圖……………………………………………16
圖1.7 FN 抹除示意圖……………………………………………16
圖1.8 Channel Hot Electron Injection寫入的示意圖…… 17
圖1.9 Band to Band Hot Hole Injection抹除的示意圖……17
第二章
圖2.1 電容結構-等效穿隧層製程流程圖……………………… 22
圖2.2 電容結構-離子轟擊製程流程圖………………………… 25
圖2.3 電容結構-電荷儲存層製程流程圖……………………… 26
圖2.4 電容結構-阻擋氧化層製程流程圖……………………… 27
圖2.5 電容結構-定義電極位置製程流程圖…………………… 28
圖2.6 初始VFB…………………………………………………… 32
圖2.7 不同電壓寫入速度比較……………………………………33
圖2.8 抹除速度比較………………………………………………34
圖2.9 未經離子轟擊之薄膜剖面…………………………………35
圖2.10 離子轟擊過後之薄膜剖面…………………………………35
圖2.11 未經離子轟擊之薄膜表面 ……………………………… 36
圖2.12 離子轟擊過後之薄膜表面 ……………………………… 36
圖2.13 比較不同偏壓下VFB飄移量之長條圖…………………… 37
圖2.14 電荷儲存能力比較…………………………………………38
表目錄
第一章
表1.1 快閃記憶體國際半導體技術藍圖列表……………………4

[1] S. Lai, Future Trends of Nonvolatile Memory
Technology, December 2001.
[2] S. Aritome, “Advanced Flash Memory Technology and
Trends for File Storage Application”, IEEE IEDM Tech.
Dig, pp. 763-766, 2000
[3] Process Integration, Device and Structures and
Emerging Research Devices, ITRS, 2009 edition.
[4] M. K. Cho and D. M. Kim, “High performance SONOS
memory cells free of drain turn-on and over-erase:
Compatibility issue with current flash technology”,
IEEE Electron Device Lett, vol. 21, pp. 399-401, Aug.
2000.
[5] F. R. Libsch and M. H. White, “Nonvolatile
semiconductor memory technology”, in SONOS Nonvolatile
Semiconductor Memories, W. D. Brown and J. E. Brewer,
Eds. Piscataway, NJ: IEEE Press, 1998, pp.309-357.
[6] S. K. Sung, I. H. Park, C. J. Lee, Y. K. Lee, J. D.
Lee, B. G. Park, S. D. Chae, and C. W. Kim,
“Fabrication and Program/Erase Characteristics of 30-
min SONOS Nonvolatile Memory Device ”, IEEE
Transaction on Nanotechnology, Vol. 2, pp. 258-264,
2003.
[7] C. S. Hsieh, P. C. Kao, C. S. Chiu, C. H. Hon, C. C.
Fan, W. C. Kung, Z. W. Wang, and E. S. Jeng, “ NVM
Characteristics of Single-MOSFET Cell Using Nitride
Spacers With Gate-to-Drain NOI” , IEEE Trans. Electron
Devices, vol. 51, pp. 1811-1817, 2004
[8] Y. S. Shin, “Non-Volatile Memory Technologies for
Beyond 2010”, Symposium on VLSI Cir. Dig. , pp. 156-
159, 2005
[9] D. Kahng and S. M. Sze, “A Floating Gate and Its
Application to Memory Device”, Bell Syst. Tech. J. ,
Vol. 46, p. 1288, 1967.
[10] M. H. White, D. A. Adams, J. Bu, “On the Go with
SONOS”, IEEE Circuits and Devices, vol. 16, no. 4,
pp. 22-31, 2000.
[11] M. French, H. Sathianathan, and M. H. White, “A
SONOS Nonvolatile Memory Cell for Semiconductor Disk
Application”, IEEE, Nonvolatile Memory Technology
Review, 1993, p. 70.
[12] M. French, H. Sathianathan, and M. H. White, “A
SONOS Nonvolatile Memory Cell for Semiconductor Disk
Application”, IEEE, Nonvolatile Memory Technology
Review, 1993, p. 70.
[13] J. D. Blauwe, “Nanocrystal Nonvolatile Memory
Devices”, IEEE Transaction on Nanotechnology, Vol. 1.
pp. 72-77, 2002
[14] W. J. Tsai, N. K. Zous, C. J. Lie, C. C. Liu, C. H.
Chen, T. Wang, “Data retention behavior of a SONOS
type two-bit storage flash memory cell”, in IEDM
Tech. Dig. , pp.719-722, 2001
[15] M. White, Y. Yang, P. Ansha, and M. L. French, “A
low voltage SONOS nonvolatile semiconductor memory
technology”, IEEE Electron Device Lett, vol. 8, pp.93-
95, Mar. 1987.
[16] T. Y. Chan, K. K. Young, and C. Hu, “A true single-
transistor oxide-nitride-oxide EEPROM device”, IEEE
Electron Device Lett, vol. 8, pp. 93-95, Mar. 1987.
[17] M. K. Cho and D. M. Kim, “High performance SONOS
memory cells free of drain turn-on and over-erase:
Compatibility issue with current flash technology”,
IEEE Electron Device Lett, vol. 21, pp.399-401, Aug.
2000.
[18] J. Bu, M. H. White, “Design Considerations in Scaled
SONOS Nonvolatile Memory Devices”, Sherman Fairchild
Laboratory, 16A Memorial Dr. E. , Lehigh University,
Bethlehem.
[19] M. She, H. Takeuchi, and T. J. King, “Silicon-
Nitride as a Tunnel Dielectric for Improved SONOS-Type
Flash Memory”, IEEE Electron Device Lett, vol.24,
pp. 309-311, 2003
[20] Jiankang Bu and Marvin H. White, “Electrical
characterization of ONO triple dielectric in SONOS
nonvolatile memory devices ”, Solid-State Electronics
45, pp. 47-51 (2001).
[21] W. J. Tsai, N. K. Zous, T. Wang, Y. H. Joseph Ku, and
C. Y. Lu, “A Novel Operation Method to Avoid
Overerasure in a Scaled Trapping-Nitride Localized
Charge Flash Memory Cell and Its Application for
Multilevel Programming”, IEEE Trans Electron Devices,
vol. 53, pp. 808-814, 2006.
[22] M. She, T. J. King, C. Hu, W. Zhu, Z Luo, J. P. Han,
and T. P. Ma,“JVD Silicon Nitride as Tunnel
Dielectric in p-channel Flash Memory”, IEEE Electron
Device Lett., Vol. 23, pp. 91-93, 2002
[23] H. Reisinger. M. Franosch, B. Hasler, and T. Bohm,
“A Novel SONOS Structure For Nonvolatile Memories With
Improved Data Retention”, Symp. on VLSI Tech. Dig. ,
pp. 113-114, 1997
[24] Y. K. Lee, S. K. Sung, J. S. Sim, C. J. Lee, T. H.
Kim, S. H. Lee, J. D. Lee, B. G. park, D. H. Lee, and
Y. W. Kim, “Multi-level Vertical Channel SONOS
Nonvolatile Memories on SOI”, Symp. on VLSI Tech.
Dig. , p. 208, 2002
[25] Y. C. King, T. J. King, and C. Hu, “A Long-Refresh
Dynamic/Quasi-nonvolatile Memory Device with 2-nm
Tunneling Oxide”, IEEE Electron Device Lett, Vol. 20,
pp. 409-411, 1999
[26] S. S. Chum, C. M. Yih, S. T. Liaw, Z. H. Ho, S. S.
Wu, C. J. Lin, D. S. Kuo, and M. S. Liang, “A Novel
High Performance and Reliability p-Type Floating Gate
N-Channel Flash EEPROM”, VLSI Tech, Symp. , pp. 19-
20, 1999
[27] W. J. Tasi, N. K. Zous, T. Wang, Y. H. Joseph Ku, and
C. Y. Lu, “A Novel Operation Method to Avoid
Overerasure in a Scaled Trapping-Nitride Localized
Charge Storage Flash Memory Cell and Its Application
for Multilevel Programming”, IEEE Trans. Electron
Devices, vol. 53, pp.808-814, 2006
[28] M. Specht, U. Dorda, L. Dreeskomfeld, J Kretz, F.
Hofmann, M. Stadele, R. J. Luyken, W. Rosner, H.
Reisinger, E. Landgraf, T. Schulz, J. Hartwich, R.
Kommling, and L. Risch, “20nm tri-gate SONOS memory
cells with multi-level operation”, in IEDM Tech.
Dig. , pp. 1083-1085, 2004
[29] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and
D. Buchanan, “Volatile and nonvolatile memories in
silicon with nano-crystal storage”, in IEDM Tech.
Dig. , pp. 521-524, 1995
[30] Jan De Blauwe, “Nanocrystal Nonvolatile Memory
Devices”, IEEEE Trans. Nanotechnology, Vol. 1, No. 1.
2002
[31] E. Lusky, Y.Shacham-Diamand, I. Bloom, B. Eitan,
“Electrons retention model for localized charge in
oxide-nitride-oxide (ONO) dielectric”, IEEE Electron
Dev. Lett. , vol.23, pp. 556-558, 2002
[32] Ying Qian Wang, Wan Sik Hwang, Gang Zhang,
“Electrical Characteristics of Memory Devices With a
High-k HfO2 Trapping Layer and Dual SiO2/Si3N4
Tunneling Layer”, IEEE Transactions On Electron
Devices, Vol. 54, No. 10, October 2007