臺灣博碩士論文加值系統

在本論文中，吾人針對利用能帶間穿隧效應(band-to-band tunneling)作為操作機制的穿隧電晶體元件進行研究。為了瞭解此新穎元件的基本特性與設計考量，吾人針對源極端接面輪廓與缺陷輔助穿隧效應(trap-assisted tunneling)對於本體穿隧電晶體元件(bulk TFET)的影響進行探討。為更進一步提升穿隧式電晶體元件的性能，吾人提出一種與互補式金屬氧化物半導體(CMOS)製程相容的磊晶穿隧層(epitaxial tunnel layer)穿隧電晶體元件。同時藉由電腦輔助設計模擬軟體(TCAD simulation)深入探討互補式穿隧電晶體(CTFETs)的各項元件參數。吾人同時展示了使用互補式穿隧電晶體架構作為反相器(inverter)的特性，並與使用互補式全耗盡型絕緣層覆矽(Fully depleted siicon-on-insulator) 金屬氧化物半導體電晶體(MOSFETs)反相器做比較。此外，吾人也同時實際製作互補式鍺磊晶穿隧層穿隧電晶體並探討其特性。
吾人首先針對源極端接面輪廓與缺陷輔助穿隧效應對於本體穿隧電晶體元件的影響進行探討。藉由不同的源極端接面輪廓比較，吾人發現靠近閘極介面層的參雜濃度與輪廓對於穿隧電晶體有最大的影響。穿隧效率與穿隧方向同時也會受到源極端接面輪廓的影響。由於缺陷在空乏區對於元件的特性會有最大的影響，因此缺陷在靠近閘極介面與接面邊緣會最劣化穿隧電晶體的特性。
了解穿隧電晶體基本特性與設計考量之後，吾人提出一種與互補式金屬氧化物半導體製程相容的磊晶穿隧層穿隧電晶體元件來提升穿隧電晶體的特性。考量到製程整合與材料特性的因素，吾人採用鍺-矽異質材料系統來驗證磊晶穿隧層穿隧電晶體的概念。藉由結構工程與磊晶穿隧層能帶工程，鍺磊晶穿隧層P型穿隧電晶體可達到優異的元件性能。
為了達成互補式穿隧電晶體的結構，吾人針對鍺磊晶穿隧N型穿隧電晶體進行研究。由於使用具有價帶位移(valence band offset)的鍺-矽異質材料系統，鍺磊晶穿隧層N型穿隧電晶體可應用抑制低電場能帶間穿隧的概念。吾人利用電腦輔助模擬軟體來展示並探討此抑制概念，同時可發現鍺磊晶穿隧層電晶體的次臨界擺幅(Subthreshold swing)特性可得到進一步提升。
吾人也對於互補式穿隧電晶體架構作為反相器的特性進行探討並同時比較使用互補式全耗盡型絕緣層覆矽金屬氧化物半導體電晶體架構作為反相器的性能。在操作電壓小於0.4 V的時候，穿隧電晶體反相器具有較快的速度。然而由於較大的寄生電容效應，穿隧電晶體反相器有較高的功率耗損。根據功率-延遲的分析，穿隧電晶體反相器操作在0.2 V時可有較快的速度同時具有較低的功率損耗。
最後，吾人同時實際製作互補式鍺磊晶穿隧層穿隧電晶體並對其進行探討。鍺磊晶穿隧層P型穿隧電晶體具有高穿隧電流、低漏電流以及良好的平均次臨界擺幅特性(約100 mV / decade 持續到10 nA / μm)。吾人也針對閘極-源極電容進行研究並同時探討其原因以及可能的影響。

In this dissertation, tunnel field-effect-transistor (TFET) utilizing band-to-band tunneling (BTBT) as the operation mechanism is studied. To realize the basic characteristics and the design issues for the novel device, the effects of the source junction profiles and the trap-assisted tunneling (TAT) on the bulk TFET are investigated. To further improve the TFET performance, a CMOS process compatible TFET with epitaxial tunnel layer (ETL) structure is proposed. Various device parameters of complementary ETL TFETs (CTFETs) are studied and discussed in detail by the TCAD simulation. The inverter characteristics based on the proposed CTFETs are also presented and compared with the inverter based on complementary fully depleted silicon-on-insulator MOSFET (CMOSFETs). Moreover, complementary Ge ETL TFETs are also fabricated and discussed.
The effects of source junction profiles and the TAT on the bulk TFET are firstly investigated. By comparing with different source junction profiles, it indicates that the doping concentrations and profiles near the gate dielectric interface have the largest influence on TFET characteristics. The tunneling efficiency and orientation are also affected by the source junction profiles. Because the defects located within the depletion region have the largest effect on the device characteristics, the defects located near the gate interface and the junction edge degrade the TFET characteristics the most.
After realizing the basic characteristics and design issues of TFET devices, a CMOS process compatible TFET with ETL structure is proposed to improve the TFET performance. Considering the process integration and material properties, Ge/Si hetero-material system is used to demonstrate the concept of the ETL TFET. Excellent device performance of Ge ETL pTFET is achieved by the structural engineering and the ETL band engineering.
To achieve the configuration of complementary TFETs, Ge ETL nTFET is investigated. Because the Ge/Si hetero-material system with the valence band offset is applied, the concept of the suppression of the low electric field BTBT (LE BTBT) can apply on the Ge ETL nTFET. The LE BTBT suppression concept is illustrated and discussed by the TCAD simulation. The S.S. characteristic of Ge ETL nTFET can be further improved.
The TFET-based inverter are also studied and compared with the MOSFET-based inverter. Better speed performance can be achieved as the VDD is below 0.4 V. However, high power consumption on the TFET-based inverter is observed due to the large parasitic capacitance of CTFETs. According to the power-delay analysis, TFET-based inverter exhibits not only better performance but also less power consumption as it is operated at 0.2 V.
Finally, complementary Ge ETL TFETs are fabricated and discussed. The fabricated Ge ETL pTFET exhibits high tunneling current, ultralow OFF-state current, and good average subthreshold swing (S.S. ~100 mV/decade up to 10 nA / μm). The gate-to-source (CGS) capacitance is also investigated. The origin and the possible influence of the CGS are also discussed.

Abstract (Chinese)…………………………………………………….i
Abstract (English)……………...……………………………………iii
Acknowledges……………………………………….……………….vi
Contents………………………………………………………….…viii
List of Tables……………………………………….………………xii
List of Figures…………………………………….…………….…xiii

Chapter 1
Introduction 1
1-1 Power Consumption on CMOS Technology 1
1-2 Steep-Slope Devices 2
1-3 Development of Tunnel FET 4
1-4 Thesis Organization 6

Chapter 2
Source Junction Profile and Defect Effect on Bulk Tunnel Field-Effect Transistor Characteristics 9
2-1 Introduction 9
2-2 Device Fabrication 10
2-3 Simulation Structure and Physical Model 11
2-4 Results and Discussion 13
2-4-1 Fabricated TFET Characteristics 13
2-4-2 Source Doping Profile Effect 14
2-4-3 Defect Position Effect 17
2-5 Conclusions 19
Chapter 3
A Simulation Study of P-channel Germanium Epitaxial Tunnel Layer Tunnel Field-Effect Transistor 38
3-1 Introduction 38
3-2 Device Design Concept 38
3-2-1 Structural Engineering 39
3-2-2 ETL Band Engineering 39
3-3 Simulation Structure and Physical Model 40
3-4 Results and Discussion 41
3-4-1 ETL Structural Engineering Improvement 41
3-4-2 ETL Band Engineering Improvement 41
3-4-3 ETL Thickness Effect 42
3-4-4 ETL Doping Effect 43
3-4-5 Gate-to-source Overlap Length Effect 44
3-4-6 Doping Concentration and Lateral Dopant Diffusion Effect 45
3-4-7 Gate-to-drain Overlap Length Effect 46
3-4-8 Quantum Confinement Effect 46
3-4-9 Summary 48
3-5 Conclusions 49

Chapter 4
A Simulation Study of N-channel Germanium Epitaxial Tunnel Layer Tunnel Field-Effect Transistor 61
4-1 Introduction 61
4-2 Low Electric Field BTBT Suppression Concept 62
4-3 Device Design Discussion 63
4-3-1 ETL Thickness Effect 63
4-3-2 ETL Doping Effect 64
4-3-3 Gate-to-source Overlap Length Effect 65
4-3-4 Doping Concentration and Lateral Dopant Diffusion Effect 66
4-3-5 Gate-to-drain Overlap Length Effect 66
4-3-5 Hetero-material System 67
4-3-6 Quantum Confinement Effect 68
4-3-7 Summary 68
4-4 Conclusions 69

Chapter 5
An Inverter Analysis of Complementary Germanium Epitaxial Tunnel Layer Tunnel Field-Effect Transistors 83
5-1 Introduction 83
5-2 Simulation Process Flow 83
5-3 Simulation Method 85
5-4 Device Characteristics 86
5-5 Inverter Analysis 87
5-5-1 Static Behavior 87
5-5-2 Dynamic Behavior 89
5-6 Summary 91

Chapter 6
Fabrication and Electrical Characteristics of Germanium Epitaxial Tunnel Layer Tunnel Field-Effect Transistors 103
6-1 Introduction 103
6-2 Device Fabrication 104
6-3 Results and Discussion 107
6-3-1 Basic Device Characteristics 107
6-3-2 Low Temperature Measurement Analysis 109
6-3-3 Capacitance Measurement Analysis 111
6-4 Conclusions 114

Chapter 7
Final Discussion and Future Recommendations 134
7-1 Summary 134
7-2 Perspectives of TFET Design 136
7-2 Future Works 138

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