臺灣博碩士論文加值系統

過去電路為了追求輸出訊號的準確度，加上了許多元件來消除原有電路的缺點，造成了電路的龐大化。而不精準的輸出訊號來源主要是因為寄生效應的問題，即積體電路中導線與導線之間存在寄生電容與漏電流，如何把寄生效應降到最低為本文所研究的方向。
現有的積體電路中存在主動元件、電容與電感三種元件，雖然積體電路中電感尚在研究中，但始終趕不及IC製程縮小的速度，現今為如何減少電阻、電容與主動元件的寄生效應。如主動元件有兩個輸入端，而設計的電路只需從其中一端輸入，則不需要選擇雙端輸入的元件，故主動元件越小寄生效應越小。如電阻器浮接，則兩端皆有寄生效應，一端接地則寄生效應只有浮接的一半，電容器也相同，故選擇設計的接地電阻器與電容器在寄生電阻與電容同位置可有效的降低寄生效應，而浮接元件有改變或影響輸出訊號，比接地元件的寄生效應大。電路中的節點同樣存在寄生效應，節點數越少寄生效應越小。根據以上要點，使用的元件越少而可達到精準的輸出訊號即為本文所追求的電路設計目標。
近幾十年來，以電流傳輸器(Current Conveyor)設計主動濾波電路已受到國際研究學者廣泛的注目與研究。本論文是使用第二代電流控制傳輸器(Second-Generation Current Controlled Conveyor, CCCII)為主動元件來設計三輸入單輸出之萬用濾波電路。因電阻器在IC中無法設計的很精準，但這種主動元件具有可用偏壓電流控制輸入端本質內阻的特性，在電路設計上可不需使用到電阻器。
在三輸入單輸出之電流式萬用濾波電路部份，我們提出以一個使用兩個負型的第二代電流控制傳輸器及一個電阻和兩個接地電容設計出二階電流式萬用濾波電路。此電路有下列優點： 1.使用最少的主被動元件， 2.二階電路中所使用的電容數及電阻數最少， 3.電容均接地，寄生效應比浮接電容小， 4.可由同一結構產生低通、帶通、高通、帶拒及全通濾波信號， 5.低的主、被動元件靈敏度， 6.諧振角頻率 與品質因素Q正交可調， 7.功率消耗低， 8.雜訊最低， 9.IC製作面積最少， 10.所需成本最低。
最後，對於本論文所提之電路，均以H-spice軟體進行電路模擬，所使用製程參數為TSMC035μm，並於實際模擬結果與理論之間相互得到驗證。

In the past circuit to reach output signal accuracy, usually increase many element reduce the disadvantage in circuit original. This result cause the circuit become complex. The major problem of non-accuracy output signal is parasitic effect, it means that integrated circuit (IC) have parasitic capacitance and leak current in wire to wire. This thesis research is how to reduce parasitic effect to lowest.

There are active element, capacitance and inductance in present integrated circuit, although inductance in integrated has be researched, but its speed can not approach reduction in IC process. Today is how to reduce the parasitic effect of resistance, capacitance and active element. If active element have two input, but the design circuit only need one input, it have no need for two input element. Chose small active element can reduce parasitic effect. If resistance floating, two terminal have parasitic effect, ground resistance have parasitic effect in one terminal, capacitance are the same. Chose ground capacitance and ground resistance with parasitic capacitance and parasitic resistance in the same terminal can reduce parasitic effect. It have parasitic effect in circuit terminal, so design in a few terminal can get low parasitic effect. According to above, using a few element to achieve output signal accurate is the goal in this thesis.

In recent of years, using current conveyor design active filters have been attended and researched by international academician. In this is, design three input and one output universal active current-mode filter using second-generation current controlled conveyor (CCCII). This active element internal resistance, denoted by Rx, at the input terminal X can be varied by tuning its bias current. It can reduce area in integrated circuit implementation.

In three input and one output, we propose a single second-generation current controlled conveyor (CCCII), two grounded capacitors, and one resistor design current-mode universal biquadratic filter in this paper. This circuit has achieved the five following important advantages: (i) no component matching conditions, (ii) using least capacitance and resistance in biquadratic circuit, (iii) grounded capacitors have lowest noise, (iv)can realize on low-pass, band-pass, high-pass, band-reject, and all-pass filters in the same structure, (v) very low active and passive element sensitivity, (vi) orthogonal control of and Q, (vii) lowest power consumption, (viii) lowest noise, (ix) lowest area in integrated circuit implementation, (x) have good cost down.

Finally, the simulation results validate and the theory predictions of the proposed circuit are verified very well by using TSMC035 H-spice simulation with supply voltage ±1.65V.

目 錄
摘 要........................................................................I
Abstract....................................................................III
誌 謝........................................................................V
目 錄........................................................................VI
圖 目 錄...................................................................VIII
表 目 錄.....................................................................XI
第一章 緒 論..................................................................1
第二章 電流式主動元件及基本電路之簡介.........................................6
2-1 等效Nullor Model模型.....................................................6
2-2 電流傳輸器(CC)的特性......................................................9
2-2.1 第一代電流傳輸器(CCI)..................................................10
2-2.2 第二代電流傳輸器﹙CCII﹚...............................................11
2-2.3第三代電流傳輸器(CCIII).................................................16
2-3 第二代電流控制傳輸器﹙CCCII﹚............................................20
2-4 多輸出端電流式主動元件架構...............................................24
第三章 文獻回顧..............................................................29
3-1 先前學者所提出之電路.....................................................30
3-1.1 電路一.................................................................30
3-1.2 電路二.................................................................31
3-1.3 電路三.................................................................33
3-1.4 電路四.................................................................34
3-1.5 電路五.................................................................35
3-1.6 電路六.................................................................37
3-2 結論.....................................................................38
第四章 以多輸入單輸出之CCCII為主動元件設計電流式萬用二階濾波電路.............39
4-1 電路設計與實現...........................................................40
4-2 HSPICE模擬結果與電路的優點..............................................45
4-3 與過去所提出之二階濾波電路比較..........................................51
4-4 電路的操作頻率..........................................................60
4-5 非理想效應分析...........................................................63
4-6 敏感度分析...............................................................65
4-7 降低非理想效應之調整....................................................77
4-7 結論....................................................................85
第五章 結論與未來研究方向....................................................86
5-1 結 論....................................................................86
5-2 未來研究方向.............................................................87
參 考 文 獻..................................................................89
作 者 簡 歷..................................................................94


圖 目 錄
圖2.1 Nullator模型............................................................7
圖2-2(a) 正型之Norator 圖2-2(b) 負型之Norator........................7
圖2-3 Nullator 與 Norator 模型...........................................8
圖2-4 CCI之元件符號.........................................................10
圖2-5 CCI之Nullor等效模型...................................................10
圖2-6 CCII之元件符號.........................................................11
圖2-7(a) CCII之Nullor模型....................................................12
圖2-7(b) CCII之簡化Nullor模型................................................12
圖2-8(a) CCII+之內部電路結構.................................................14
圖2-8(b) CCII-之內部電路結構.................................................14
圖2-9 CCII之簡單應用.........................................................15
圖2-10 CCIII之元件符號.......................................................17
圖2-11 以雙輸出之CCII實現CCIII...............................................17
圖2-12(a)電流加法器..........................................................17
圖2-12(b)加權電流加法器......................................................18
圖2-13(a)電流放大器..........................................................18
圖2-13(b)電壓放大器..........................................................18
圖2-13(c) 傳輸阻抗放大器.....................................................18
圖2-13(d) 傳輸導納放大器.....................................................19
圖2-14 CCIII之CMOS內部電路...................................................19
圖2-15 CCCII之元件符號及Nullor模型...........................................20
圖2-16(a) CCCII+之內部電路...................................................22
圖2-16(b) CCCII-之內部電路...................................................22
圖2-17 CCCII之基本應用電路...................................................23
圖2-18複製正向電流源及反向電流源.............................................25
圖2-19疊接電路複製正向電流源及反向電流源.....................................25
圖2-20 CCCII(-/-)之電路符號及端點特性........................................26
圖2-21 CCCII(-/-)之內部電路圖................................................26
圖2-22 CFCCCIIp之電路符號及端點特性..........................................27
圖2-23 CCCII(+/-)之內部電路圖................................................27
圖2-24 DO-CCCII之Nullor模型..................................................28
圖3-1 Muhammad T.A和Noman A T.於1998年所提出之單輸入三輸出電路...............30
圖3-2 Shahram Minaei和Sait Turkoz於2001年所提之電流式單輸入三輸出的濾波電路......32
圖3-3 IQBAL A.K.和MEHMOOD H.Z.發表的單輸入三輸出濾波電路.....................33
圖3-4 M. Sagbas和K. Fidanboylu發表的單輸入三輸出濾波電路.....................34
圖3-5 Neeta Pandey, Sajal K. Paul和Asok Bhattacharyya發表的三輸入三輸出濾波電
路...........................................................................36
圖3-6 Tatsuya Katoh , Takao Tsukutani, Yasuaki Sumi 和Yutaka Fukui發表的三輸入
三輸出濾波電路...............................................................37
圖4-1 被動元件所產生的寄生電阻與寄生電導.....................................39
圖4-2 與 節點所對應的電路...................................................42
圖4-3 新的電流式單輸入三輸出萬用二階路波電路.................................43
圖4-4 Low-pass頻率響應(500kHz與1MHz).........................................46
圖4-5 1MHz時低通響應理論與模擬值比較.........................................46
圖4-6 Band-pass頻率響應(500kHz與1MHz)........................................47
圖4-7 1MHz時帶通響應理論與模擬值比較.........................................47
圖4-8 Highpass頻率響應(500kHz與1MHz).........................................48
圖4-9 1MHz時高通響應理論與模擬值比較.........................................48
圖4-10 Notch頻率響應(500kHz與1MHz)...........................................49
圖4-11 1MHz時帶拒響應理論與模擬值比較........................................49
圖4-12 Allpass頻率響應相位圖(500kHz與1MHz)...................................50
圖4-13 1MHz時全通響應理論與模擬值比較........................................50
圖4-14 Muhammad T.A和Noman A T.於1998年所提出之單輸入三輸出電路..............53
圖4-15 學者Muhammad T.A和Noman A T.所提二階濾波電路之低通、帶通、高通頻率響應模
擬與理論值對照圖.............................................................54
圖4-16 IQBAL A.K.和MEHMOOD H.Z.發表的單輸入三輸出濾波電路....................54
圖4-17學者IQBAL A.K.與MEHMOOD H.Z.所提二階濾波電路之低通、帶通、高通頻率響應模
擬與理論值對照圖.............................................................55
圖4-18 M. Sagbas和K. Fidanboylu發表的單輸入三輸出濾波電路....................56
圖4-19學者M. Sagbas和K. Fidanboylu所提二階濾波電路之低通、帶通、高通頻率響應模
擬與理論值對照圖.............................................................57
圖4-20 Neeta Pandey, Sajal K. Paul和Asok Bhattacharyya發表的三輸入三輸出濾波路..........58
圖4-21(a) 學者Neeta Pandey, Sajal K. Paul與Asok Bhattacharyya所提二階濾波電路低
通、帶通、高通、帶拒頻率響應模擬與理論值對照圖...............................59
圖4-21(b) 學者Neeta Pandey, Sajal K. Paul與Asok Bhattacharyya所提二階濾波電路全
通頻率響應模擬與理論值對照圖.................................................60
圖4-22 低通濾波電路頻率響應10Hz到302MHz......................................61
圖4-23 帶通濾波電路頻率響應10Hz到110MHz......................................61
圖4-24 高通濾波電路頻率響應10Hz到66MHz.......................................62
圖4-25 帶拒濾波電路頻率響應10Hz到77.6MHz.....................................62
圖4-26 全通濾波電路頻率響應10Hz到179.8MHz....................................63
圖4-27 CCCII負型雙端輸出非理想模型...........................................64
圖4-28(a) Lowpass Gx、G、C1與C2＋10%輸出頻率響應.............................67
圖4-28(b) Lowpass Gx、G、C1與C2＋10%輸出頻率響應局部放大.....................67
圖4-29(a) Bandpass Gx、G、C1與C2＋10%輸出頻率響應............................68
圖4-29(b) Bandpass Gx、G、C1與C2＋10%輸出頻率響應局部放大....................68
圖4-30(a) Highpass Gx、G、C1與C2＋10%輸出頻率響應............................69
圖4-30(b) Highpass Gx、G、C1與C2＋10%輸出頻率響應局部放大....................69
圖4-31(a) Notch Gx、G、C1與C2＋10%輸出頻率響應...............................70
圖4-31(b) Notch Gx、G、C1與C2＋10%輸出頻率響應局部放大.......................70
圖4-32(a) Allpass Gx、G、C1與C2＋10%輸出頻率響應.............................71
圖4-32(b) Allpass Gx、G、C1與C2＋10%輸出頻率響應局部放大.....................71
圖4-33 Low-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度......................72
圖4-34 Low-pass Gx、R1、C1與C2增加10%時之最大值敏感度........................73
圖4-35 Band-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度.....................73
圖4-36 Band-pass Gx、R1、C1與C2增加10%時之最大值敏感度.......................74
圖4-37 High-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度.....................75
圖4-38 High-pass Gx、R1、C1與C2增加10%時之最大值敏感度.......................75
圖4-39 Notch Gx、R1、C1與C2增加10%時之操作頻率敏感度.........................76
圖4-40 All-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度......................77
圖4-41 1MHz時調整前與經過調整(Tuning)後的低通響應(實線為調整前、虛線為調整後)..........79
圖4-42 1MHz時調整前與經過調整(Tuning)後的帶通響應(實線為調整前、虛線為調整後)..........80
圖4-43 1MHz時調整前與經過調整(Tuning)後的高通響應(實線為調整前、虛線為調整後)..........82
圖4-44 1MHz時調整前與經過調整(Tuning)後的帶拒響應(實線為調整前、虛線為調整後)..........83
圖4-45 1MHz時調整前與經過調整(Tuning)後的全通響應(實線為調整前、虛線為調整後)..........84


表 目 錄
表2-1 CCII之工作電壓及電流的範圍.............................................13
表2-2 CCII其MOS電晶體之長寬比值..............................................13
表4-1 頻率為500kHz與1MHz時Low-pass、Band-pass、High-pass、Notch所使用之元件值..........45
表4-2 頻率為500kHz與1MHz時All-pass所使用之元件值.............................45
表4-3 500kHz與1MHz 時Low-pass各參數值........................................46
表4-4 500kHz與1MHz 時Band-pass各參數值.......................................47
表4-5 500kHz與1MHz 時High-pass各參數值.......................................48
表4-6 500kHz與1MHz 時Notch各參數值...........................................49
表4-7 500kHz與1MHz 時All-pass各參數值........................................50
表4-8 電路特性與元件比較表...................................................52
表4-9 輸出信號模擬結果與理論值誤差表.........................................53
表4-10 輸出信號模擬結果與理論值誤差表........................................55
表4-11 輸出信號模擬結果與理論值誤差表........................................57
表4-12 輸出信號模擬結果與理論值誤差表........................................59
表4-13 Lowpass Gx、R1、C1與C2增加10%時之操作頻率敏感度.......................72
表4-14 Low-pass Gx、R1、C1與C2增加10%時之最大值敏感度........................72
表4-15 Band-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度.....................73
表4-16 Band-pass Gx、R1、C1與C2增加10%時之最大值敏感度.......................74
表4-17 High-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度.....................74
表4-18 High-pass Gx、R1、C1與C2增加10%時之最大值敏感度.......................75
表4-19 Notch Gx、R1、C1與C2增加10%時之操作頻率敏感度.........................76
表4-20 All-pass Gx、R1、C1與C2增加10%時之操作頻率敏感度......................76
表4-21 1Mhz時Lowpass轉導值(Gx)和R與操作頻率及最大值關係......................78
表4-22 1MHz時調整後的低通響應設定參數值及響應量測參數值......................79
表4-23 1Mhz時Bandpass轉導值(Gx)和R與操作頻率及最大值關係.....................79
表4-24 1MHz時調整後的帶通響應參數值及響應量測參數值..........................80
表4-25 1Mhz時Highpass轉導值(Gx)和R與操作頻率及最大值關係.....................81
表4-26 1MHz時調整後的高通響應參數值及響應量測參數值..........................81
表4-27 1Mhz時Notch轉導值(Gx)和R與操作頻率及最大值關係........................82
表4-28 1MHz時調整後的帶拒響應參數值及響應量測參數值..........................83
表4-29 1Mhz時Allpass轉導值(Gx)和R與操作頻率及相位關係........................83
表4-30 1MHz時調整後的全通響應參數值及響應量測參數值..........................84

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