臺灣博碩士論文加值系統

本論文主要討論應用於WiMAX系統之具干擾偵測功能射頻前端接收器設計。本文提出一個干擾偵測的機制，可應用於偵測干擾訊號的大小相對於系統想要的訊號。同時也提出具有可控制的雙模線性度(高線性度: 高耗電 ; 低線性度: 低耗電)的射頻前端接收器。將上述電路整合，可在環境干擾大於某個程度時，干擾偵測機制可控制射頻前端接收器於高線性度模式; 反之，則控制於低線度模式。高線性度模式比低線性度模性在射頻接收器的系統模擬上，多增加了5.5dB的干擾容忍值。此系統架構電路是以 0.18 微米 CMOS製程實現。

In this paper, an interference aware scheme is proposed with RF receiver front-end design for WiMAX application. The interference level can be sensed via the proposed scheme for the adjustment of RF front-end linearity performance which corresponds to the system interference tolerance hence avoids unnecessary power consumption. A RF receiver front-end including a low noise amplifier and a mixer with dual modes of high linearity and low linearity are applied to demonstrate the proposed interference aware scheme for WiMAX application. By applying the proposed interference aware scheme with dual modes RF front-end, 5.5dB improvement of system interference tolerance can be achieved. These circuits are fabricated in 0.18um CMOS process.

Contents

摘要 i
Abstract ii
誌謝 iii
Contents iv
List of Figures vii
List of Tables ix
Chapter 1 1
1.1 Motivation 2
1.2 Receiver Specifications 3
1.2.1 Frequency Band Selection 3
1.2.2 Receiver Specifications 4
A. Sensitivity 5
B. Adjacent and non-adjacent channel rejection 6
1.2.3 Receiver Architecture 7
1.2.4 RF Receiver Front-End Specifications Calculation 8
1.3 Previous Techniques for the Linearity Improvement 9
1.3.1 Degeneration of the Input Gm-Stage 10
1.3.2 IM3 Cancellation Techniques 11
A. Active Post-Distortion Technique 11
B. IM3 Cancellation by Duplicate Circuit 12
1.3.5 Summary 13
1.4 The Concept of Rx Front-End with IAS 14
1.5 Power Efficiency Analysis 15
1.6 Organization 16
Chapter 2 17
2.1 Design Concepts of RX Front-end with IAS 17
2.1.1 Determine Threshold S 17
2.1.2 The Behavior of the IAS 18
2.2 The Components of the IAS 19
A. Signal Distinction 20
B. Envelop Detection 21
C. Error Correction 22
D. Mode Selection 23
2.3 The Design Flow of the IAS 24
A. Adaptive Threshold S 24
B. Sensitivity Issues 25
C. Gain Difference 25
Chapter 3 26
3.1 RX Front-End Circuit Design 26
3.1.1 System View 26
3.1.2 Circuit View 27
3.1.3 Circuits and Summary 28
3.1.4 System Co-simulation 29
A. Co-simulation Platform 29
B. Simulation Results 31
3.2 The Circuit Design of the IAS 31
3.2.1 Peak Detector, Schmitt Trigger, and Ampifier 32
A. Peak Detector 32
B. Schmitt Trigger and Amplifiers 33
C. Sensitivity Issue 33
3.2.2 The Design Flow of the IAS 34
A. Adaptive Threshold S 34
B. Sensitivity Issues 34
C. Gain Difference 34
3.2.3 Amplifiers with CMFB (Amp_I & Amp_S) 34
3.2.4 5th-order Elliptic Filter 36
A. 1. Linearity Technique: 37
B. High Output Impedance Technique for Gm cell 38
3.2.5 Summary 40
3.3 Analysis of the I/Q Mismatch Due to IAS 41
3.4 Voltage Offset Analysis 43
3.5 Power Efficiency Analysis 44
Chapter 4 45
4.1 RF Receiver Front-End 45
4.1.1 Layout Consideration 45
A. Chip Layout 46
B. PCB Layout 47
4.1.2 Measurement 48
A. DC 48
B. S-parameter 50
C. Power Gain 51
D. IIP3 53
E. NF 54
4.1.3 Summary 55
4.2 Interference Aware Scheme 56
4.2.1 Layout Consideration 56
A. Chip Layout 56
B. PCB Layout 57
4.2.2 Measurement 57
A. DC 58
B. Two-Tone Test 59
Chapter 5 60
5.1 Summary 60
5.2 Future Works 60
5.2.1 Fully Integrated Chip 60
5.2.2 Dynamic Range of the IAS 62
Bibliography 64
Vita 65

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