臺灣博碩士論文加值系統

在無線感測網路的應用中，功率消耗為重要的考量之一，為了延長這些應用的使用時間，會需要低功率的系統晶片，而在這些系統晶片的功率消耗中，又以隨機存取記憶體佔極大部分，為了能夠降低功率消耗，至今已經提出了許多低功率技巧，其中調降電壓至近臨界電壓或次臨界電壓為非常有效的方法之一，然而在近臨界電壓及次臨界電壓的操作中，會遭遇更嚴重的變異。以去耦讀取埠的隨機存取記憶體而言，在進行讀取時，會因為變異使得漏電流與維持電路電流的比例有大幅度變動導致產生讀取錯誤。在本篇論文中，為解決這些變異造成的讀取錯誤，提出了本地欄位偵測維持電路來偵測變異，並自適應性的產生維持電路電流，使次臨界電壓操作的讀取能夠正確，同時藉由降低讀取時的抵抗電流來達到降低功率消耗的優勢。本論文提出的電路以台積電90奈米製程下線並做佈局後模擬驗證，能將操作電壓降低至近臨界與次臨界電壓，並與現今的技術相比，在漏電流最大的情況能降低24%的功率。

Power consumption is one of important issues in power constraint applications such as wireless sensor networks (WSN). For these power constraint applications, we need a low power system-on-a-chip (SoC) to extend life time. In breakdown of power consumption, SRAMs are one of major sources of power consumption in the SoC. Scaling supply voltage into near-threshold or sub-threshold region is one of effective techniques to reduce power consumption. However, severe variations may occur in the near-threshold and the sub-threshold region. For a read-decoupled SRAM, read failures may happen because the current ratio between a keeper and a pull-down network has large variations. In this thesis, we propose a local column sensing keeper scheme to detect the variations and adaptively generate a proper keeper current to deal with the read functionality issues. Meanwhile, power consumption is reduced by minimizing the keeper contention current. A test chip is fabricated using TSMC 90nm technology to demonstrate the proposed SRAM. According to post-layout simulation results, the proposed scheme supports near-threshold and sub-threshold operation and achieves 24% power reduction when compared with state-of-the-art designs in the worst leakage case.

摘 要 i
Abstract ii
致 謝 iii
Contents iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
1.1 Background 1
1.1.1 Preliminary 1
1.1.2 Sub-threshold operation 2
1.1.3 Read-decoupled 8T-SRAM 5
1.2 Motivation 7
1.2.1 Process variation 8
1.2.2 Temperature variation 9
1.3 Contributions 12
1.4 Thesis organization 12
Chapter 2 Adaptive Keeper Design 14
2.1 Variation tolerant approaches 14
2.2 Replica circuit technique 15
2.2.1 Leakage current replica keeper 15
2.2.2 Current comparison based domino 16
2.2.3 Marginal bitline leakage compensation scheme 18
2.3 Variation sensor technique 19
2.3.1 Variation tolerant keeper 20
2.4 Summary 21
Chapter 3 Proposed local column sensing keeper scheme 23
3.1 Proposed architecture 23
3.2 Proposed circuit design 26
3.2.1 Non-accessed pull-down network (PDN) 26
3.2.2 PVT variation sensing circuit 27
3.2.3 Data dependent leakage compensation circuit 28
3.2.4 Control circuit 31
3.3 Operation flow of proposed design 33
3.3.1 Read 0 operation 34
3.3.2 Read 1 operation 34
Chapter 4 Test Chip Implementation 37
4.1 Chip planning 37
4.2 SRAM design 39
4.2.1 SRAM implementation 39
4.2.2 Layout consideration 39
4.3 BIST design 43
Chapter 5 Simulation Results 45
5.1 Simulation environment setup 45
5.1.1 Simulation setup of proposed local column sensing keeper scheme 45
5.1.2 Simulation setup of comparison with MBLC 46
5.1.3 Simulation setup of test chip 46
5.1.4 Design trade-off for keeper sizing 46
5.2 Simulation results of the local column sensing keeper scheme 48
5.2.1 Analysis of PVT variation sensing circuit 48
5.2.2 Analysis of data dependent leakage compensation circuit 50
5.2.3 Analysis of mismatch 52
5.2.4 Analysis of read noise margin 53
5.3 Simulation results of MBLC 54
5.4 Simulation results of the test chip 56
5.5 Comparison 58
Chapter 6 Discussion 59
6.1 Scalability of bitline length 59
6.2 Scalability of process technology 60
Chapter 7 Conclusions and Future Works 62
7.1 Conclusions 62
7.2 Future works 63
References 64
個人簡歷 68

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