臺灣博碩士論文加值系統

本論文詳細探討了一種高速低功率唯讀記憶體編譯器的設計。在傳統的低功率唯讀記憶體電路中，Selective Bit-Line Pre-charge的架構是最常被提及用來減少動態操作電流的技巧，但大部份的論文卻忽略了此架構在減少電路的靜態漏電流上更是有其先天上的優勢。在本論文中，將詳細比較此架構與傳統電路在漏電流上的差距，並討論它在漏電嚴重的製程中的必需性。此外，為了改善此架構在速度上過慢的缺點，在本論文中也提出了一種新的架構 : 允許 word line 與 pre-charge 二種訊號相疊。根據模擬的結果，新架構會增加約 2% 的耗電，但卻能增進約 20 % 的效能。整個高速低功率唯讀記憶體的電路架構，將以記憶體編譯器實現，並支援了三種不同 Mux(16,32,64) 的組態以求達到面積與效能的最佳化。整套編譯器將可產生近11萬種的唯讀記憶體，記憶體容量可由 1024 至 2M bits，最後並將所有需驗證的記憶體，以90奈米低功率CMOS的製程出測試晶片。測試的結果顯示， 8192x32m16 (256Kb) 的唯讀記憶體可以達到幾乎與SRAM相同效能的 3.0 ns access time。靜態漏電流在1.2V/25°C時為11.41µA，動態操作電流在1.2V/25°C/100MHz 時為2.65mA。採用此電路架構可使靜態漏電流減少十倍，動態操作電流可減少五倍。

In this paper, a high-speed low-power ROM compiler is developed. In conventional low power ROM design, Selective Bit-Line Pre-charge is the most popular technique used to reduce dynamic power consumption. But most of them don’t refer to its superior advantages on leakage current reduction. In this paper, the leakage current reduction by this technique is investigated in circuits fabricated by technologies that suffer severe off-state leakage issues. Besides, a new operational scheme to improve its accessing speed is proposed, which allows word line signal to overlap with pre-charge signal. According to simulation results, the new operational scheme leads to 20% enhancement in accessing speed, at the cost of 2% increase in dynamic power. This high-speed low-power ROM architecture is implemented by using Memory Compiler. It can support 3 kinds of Mux configurations for area / speed optimization. This ROM compiler can generate 109616 kinds of ROM instances. Instances size range from 1024 to 2M bits. A test chip covers all necessary instances by 90nm CMOS low power technology is fabricated. Testing results show that the access time of 8192x32m16 (256Kb) ROM instance is 3.0 ns, which is comparable to SRAM performance. Standby current is 11.41µA at 1.2V/25°C; dynamic operation current is 2.65mA at 1.2V/25°C/100MHz. The new scheme allows for 10X standby current reduction and 5X active power reduction

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