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經過數十年的研究，二階層邏輯網路合成已是一門被充份了解及發展成熟
的科學。然而，多階層邏輯網路合成卻較少被研究，因為比較困難，而且
是比較新的技術。近年來，多階層邏輯網路合成逐漸受到青睞，原因在於
它能使多輸出布林函數共用部份邏輯網路，因而比二階層邏輯網路佔較少
晶片面積；它可以讓設計者在晶片面積與邏輯網路延遲間擇優，也就是多
階層邏輯網路合成非常有彈性。本論文提出一個多階層多輸出邏輯網路合
成方法，我們利用允許方體零壹交替法達成邏輯合成技術。應用零壹交替
法合成的反及閘邏輯網路其輸入僅需非補數型態的變數。我們將卡諾圖改
良成允許方體全及項關連圖，以突破卡諾圖六變數的限制。我們提出的允
許方體全及項關連圖非常適用於零壹交替法，可快速、容易且正確地找到
所需的允許方體。我們的邏輯合成系統有四大部分：多階層反及閘邏輯網
路合成、多階層反及閘邏輯網路階層簡化、三階層反及閘邏輯網路閘簡化
和多階層多輸出反及閘邏輯網路合成。我們應用階層簡化技術，減少邏輯
網路的延遲。我們也應用閘簡化的技術，以獲得幾近最簡的反及閘邏輯網
路。我們以Ｃ語言實現邏輯合成系統的電腦輔助設計，並做一些實驗。實
驗結果顯示我們所合成的多階層反及閘邏輯網路較以積項和方法合成的二
階層邏輯網路使用較少的邏輯閘，這也證實多階層邏輯網路較二階層邏輯
網路佔較少晶片面積。
The subject of two-level logic synthesis is well developed and
well understood. In contrast, multilevel logic synthesis is
less studied, more difficult, and relatively new. Nevertheless,
multilevel logic synthesis has received most attention by CAD
researchers, because (1) it enables circuitry sharing among the
multiple functions, (2) there is usually an area/delay tradeoff
for the implementations of a Boolean function. Namely, multi-
level logic synthesis is very flexible. This paper proposes
algorithms of synthesizing multilevel multioutput NAND gate
logic network. We use ZOI(Zero One Inter- action) of
permissible cube to achieve logic synthesis. Only
uncomplemented input variables are needed by using the ZOI al-
gorithm to synthesis NAND gate logic network. We modify Kar-
naugh map into PCRM (Permissible Cube Related Minterm) graph.
We use PCRM graph to generate and locate permissible cubes
which are required for multilevel NAND gate logic synthesis.
Our logic synthesis system includes synthesis of multilevel
NAND gate logic network, level reduction of multilevel NAND
gate logic network, gate reduction of multilevel NAND gate
logic network, and synthesis of multilevel multioutput NAND
gate logic network. The level reduction technique reduces cir-
cuit delay. The gate reduction technique eliminate redundant
gates in the synthesized NAND gate logic network. The proposed
logic synthesis system is implemented in C language. The ex-
perimental results shows that multilevel logic networks use
less gates than two-level logic networks.
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