臺灣博碩士論文加值系統

離散小波轉換的技術，已被廣泛的應用於訊號分析與影像處理的問題上。由於小波轉換後的係數呈現能量集中低頻的特性，非常適合影像資料壓縮的前處理。新的工業界標準中如JPEG2000、MPEG4已使用離散小波轉換取代離散餘弦轉換。
基於此，本論文將針對一維一層、一維多層與二維多層離散小波轉換的硬體架構，提出符合JPEG2000標準的離散小波轉換硬體設計。除了可輕易整合離散小波轉換與反轉換之外，更可以利用模組化的設計觀念，在不同的硬體架構上實現。
在本論文中，我們分別使用了二種不同的架構實現一維多層DWT。並以一維多層的硬體為基礎，配合二維控制器應用於二維多層DWT的硬體設計。
最後藉由Synopsys與Avant! tool模擬與合成實際的晶片以後，不管在圖形處理能力、運算速度或晶片面積上皆具有不錯的表現。

The discrete wavelet transform (DWT) technique has been widely used in signal processing and image processing. Since the DWT coefficients have the property of energy conservation in the low frequency part, it is suitable for data compression. In the recent industry standard, DWT has replaced DCT which is a main approach in image compression in JPEG2000 and MPEG4.
Due to the drawback, the thesis focuses on the hardware architectures of 1-layer 1- dimensional DWT, multi-layer 1-dimensional DWT and Multi-layer 2-dimensional DWT which are the standard of JPEG2000. Based on the architecture, DWT and the inverse discrete wavelet transform (IDWT) can be integrated easily. Furthermore we can use the module design concept to implement DWT by different hardware architectures.
Moreover, in the thesis, we use two different architectures to implement the multi-layer 1-dimensional DWT. Besides, accompanied with “2D-controller”the multi-layer 1-dimensional DWT can be adopted in multi-layer 2-dimension DWT hardware architecture.
Consequently, the gate level simulation and P&R are done with Synopsys and Avant! tools. The chip has advantages in the ability of image processing, execution time and chip area.

目 錄
中文摘要…………………………………………………………………………...i
英文摘要…………………………………………………………………………..ii
誌謝……………………………………………………………………………….iii
目錄……………………………………………………………………………….iv
圖目錄…………………………………………………………………………….vii
表目錄…………………………………………………………………………….xi
第一章 緒論…………………………………………………………1
1.1 研究背景……………………………………………………………1
1.2 研究動機……………………………………………………………2
1.3 論文章節安排………………………………………………………3
第二章 小波轉換理論概述…………………………………………5
2.1 一維離散小波轉換與反轉換………………………………………..5
2.2 二維離散小波轉換與反轉換………………………………………...7
2.3 二維離散小波轉換的多層解析……………………………………...9
第三章 Lifting Scheme小波轉換…………………………………..11
3.1 Lifting Scheme………………………………………………………...11
3.2 Lifting Scheme DWT計算分析………………………………………14
3.3 Lifting Scheme IDWT計算分析……………………………………...16
3.4 使用1M2A的Lifting Scheme wavelet transform架構………………18
第四章 一維多層小波轉換硬體架構設計………………………….21
4.1架構概述………………………………………………………………….21
4.1.1 ALU unit………..………………………………………………..22
4.1.1.1 暫存器陣列(register bank)…………………………….22
4.1.1.2 MAC……………………………………………………24
4.1.1.3 資料運算路徑的Pipeline……………………………...25
4.1.2 Control unit………………………………………………………26
4.1.2.1 時序產生器…………………………………………….26
4.1.2.2 濾波器係數記憶體…………………………………….27
4.1.2.3 狀態設定電路………………………………………….28
4.1.3 I/O unit…………………………………………………………...30
4.2 實現一維多層小波轉換………………………………………………..31
4.3 CDF(9,7) for JPEG2000…………………………………………………33
第五章 二維多層小波轉換硬體架構設計…………………………..37
5.1 2D-DWT實現演算法………………………………………………….37
5.2 2D-DWT/IDWT的硬體架構…………………………………………..38
5.3 DWT 2D-Controller的硬體架構………………………………………40
5.3.1 DWT Address-Generator………………………………………..41
5.3.2 暫存器陣列Register Array(for DWT)………………………….44
5.3.3 Control Set(for DWT)…………………………………………..46
5.3.4 DWT Hand-Shaking…………………………………………….48
5.4 IDWT 2D-Controller的硬體架構………………………………………49
5.4.1 IDWT Address-Generator……………………………………….50
5.4.2 暫存器陣列Register Array(for IDWT)…………………………52
5.4.3 Control Set(for IDWT)…………………………………………..54
5.4.4 IDWT Hand-Shaking……………………………………………56
第六章 晶片硬體實現………………………………………………..59
6.1 Lossless Compression二維多層離散小波轉換晶片規格Chip53…..59
6.1.1 晶片規格及佈局………………………………………………..59
6.1.2 晶片佈局圖……………………………………………………..62
6.1.3 晶片特性………………………………………………………..64
6.1.4 chip53晶片模擬結果…………………………………………..64
6.2 Lossly Compression二維多層離散小波轉換晶片規格Chip97……..67
6.2.1 晶片規格及佈局………………………………………………...67
6.2.2 晶片佈局圖……………………………………………………...69
6.2.3 晶片特性……………………………………………………...…71
6.2.4 chip97晶片模擬結果…………………………………………...71
6.3 晶片效能分析…………………………………………………………...74
第七章 結論與未來展望……………………………………………..79
7.1 結論…………………..…………………………………………………79
7.2 未來展望………………………………………………………………..80
參考文獻…………………………………………………………………………….81

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