臺灣博碩士論文加值系統

在多核心晶片的世代下，為提高晶片的傳輸效能，晶片網路(Network on Chip, NoC)被提出取代傳統匯流排通訊架構，以改善多核心系統的傳輸效能。然而，當通訊架構複雜後，在封包傳遞與通訊環境上衍生出其他問題。在封包傳遞方面，使用晶片網路可以提升封包傳輸吞吐率，但其功率消耗也相對提高，特別在行動裝置上，功率消耗的影響甚廣。此二效能指標若擇一實現會導致另一指標受影響，因此如何兼顧並實現低功率消耗與高吞吐率的設計為晶片網路重要因素；在通訊環境方面，由於傳遞單元路由器包含大量的虛擬通道(Virtual Channels, VCs)與複雜的仲裁器，當受到環境、溫度以及雜訊等影響而出現暫時性故障會導致系統效能下降，甚至導致相連接的處理單元(Processing Element, PE)失去功能。因此，本論文提出自適應式封包編解碼架構(Adaptive Instruction Codec Architecture, AICA)與具自我修復架構(Self-Healing Architecture, SHA)之路由器來解決上述所提到的問題。
本論文包含二個主要部分，分別為AICA與SHA其共同目的是改善throughput的傳輸效能，並依照此二架構不同的優點，進而改善功率消耗、延遲率以及資料遺失率。此二架構分別設計於網路介面(Network Interface, NI)中的自適應式封包編解碼架構與Router中的自我修復機制。由於在多核心系統下，其NoC所傳遞的封包中皆為指令與資料，其中指令的相似度與重複性極高，因此透過自適應式封包編解碼架構可以有效降低封包傳遞時的冗餘性來減少封包的傳遞次數，進而減少封包傳遞時的功率消耗。同時每個封包所乘載的內容也由單一變成複數內容，因此提高了通道的使用率以及吞吐率。在傳遞過程中，其網路會因不確定的干擾導致系統效能暫時或永久性降低，因此晶片上的自我修復技術針對易受影響的VCs與仲裁器進行重置，讓NoC保持理想的通訊環境。最後本論文整合AICA與SHA架構並提出整合後的新的架構AICA_SHA，不僅達成穩定與高效能的傳輸，更可改善與穩定網路的傳輸效能與功率消耗。
本論文實現環境使用Xilinx Vivado 2015.2進行設計，驗證平台為Xilinx FPGA Kintex UltraScale XCKU040-2FFVA1156E，其網路拓樸為4×4 Mesh架構。本論文先針對所設計的二個架構AICA與SHA進行獨立分析其效能，最後再分析整合後的架構效能(AICA_SHA)。在適應式封包編解碼架構的晶片網路中，功率消耗平均可以改善30.3%以及吞吐率改善23.5%。而在具自我修復機制的晶片網路中，資料遺失率平均可以改善20.68%、吞吐率改善57.57%以及延遲改善120.75%。最後在AICA_SHA架構中，功率消耗平均可以改善57.79%，資料遺失率改善46.42%，吞吐率改善208.42%以及延遲改善47.25%。從實驗中可以得知，本論文不僅兼顧功率消耗與吞吐率，更可以維持穩定的通訊品質。

In order to enhance efficient transmission in multi-core chip, the Network on Chip (NoC) was proposed to replace bus communication architecture. However, the packet access and communication environment create some issues when it uses complicated communication architecture. In the terms of packet access, the NoC can improve throughput, however, it also enhances power consumption. This result is harmful in mobile device. Therefore, achieve both of high throughput and low power consumption for the NoC are important factors. In the terms of communication environment, the router contains a large number of Virtual Channels (VCs) and complicated arbiter. Which will let to NoC performance decreases and Processing Element (PE) indirectly loses function when the transient fault was occurred by environment, temperature and noise. Thus, this dissertation proposes a packet codec architecture and self-healing mechanism for NoC to solve the above-mentioned problems.
In our dissertation, the Adaptive Instruction Codec Architecture (AICA) designed in Network Interface (NI) and Self-Healing Architecture (SHA) designed in router. Which improves the transmission efficiency of the throughput is common purpose of this two architecture. Depending on other advantages of the two architectures, the power consumption, the delay rate, and the data loss rate are improved. The transmission packet is usually instruction and data, the type of instruction have high repeatability and similarity in multi-core chip. Therefore, the AICA not only effectively reduces redundancy of packet delivery to improve flits number of passes, but also reduces the power consumption of packet transmission. Simultaneously, each flit payload from a singular into a plural, thus enhance throughput and channel utilization rate. In order to avoid uncertain interference to cause temporary or permanent reduction in system performance, therefore, this dissertation aims vulnerable VCs and arbiter to propose self-healing mechanism to maintain the ideal communication environment in NoC by reset. Finally, this dissertation integrates AICA and SHA to propose novel architecture AICA_SHA, which not only reaches a stable and efficient transmission architecture, but also improves and stabilizes the transmission efficiency and power consumption of the network.
In this dissertation, the design tool used the Xilinx Vivado 2015.2, and the emulation platform was used Xilinx FPGA Kintex UltraScale XCKU040-2FFVA1156E. The network topology used 4 × 4 Mesh architecture. In this dissertation first independently analyzes the performance of the two architectures of AICA and SHA, and then analyzes the integrated architecture (AICA_SHA). In the AICA experimental results show, the proposed architecture and algorithms deliver average improvement of 30.3% on power consumption, and 23.5% on throughput. In the SHA experimental results show, the proposed mechanism delivers average improvement of 57.57% on throughput, 20.68% on data loss, and 120.75% on latency. Finally, the AICA_SHA experimental results show, the proposed architecture delivers average improvement of 57.79% on power consumption, 46.42% on data loss, 208.42% on throughput, and 47.25% on latency. The experimental results show that this dissertation not only improves power consumption and throughput, but also maintain stable communication quality.

CONTENTS
摘要 i
ABSTRACT iii
誌 謝 vi
CONTENTS viii
LIST OF TABLES xii
LIST OF FIGURES xiv
Chapter 1 Introduction 1
1.1 NoC Infrastructure 2
1.1.1 NoC with Mesh Topology Architectures 2
1.1.2 Router Architectures 3
1.1.3 Flit Format 5
1.2 Problem Definition 6
1.2.1 Flits Transmission Affects Performance 6
1.2.2 Transient Faults Affects Performance 7
1.3 Performance Analysis and Solutions 11
1.3.1 Flits Transmit Issues 12
1.3.2 Transient Faults Issues 13
1.4 Motivation 15
1.5 Contributions 16
1.6 Organizations 18
Chapter 2 Background and Related Works 19
2.1 Packet-Switching Topologies 19
2.1.1 Store and Forward 19
2.1.2 Virtual Cut Through 20
2.1.3 Wormhole 20
2.2 Routing Algorithm Approaches 21
2.2.1 Deterministic Routing 21
2.2.2 Adaptive Routing 23
2.3 Improve Performance Technologies on NoC 24
2.3.1 Power Saving Technologies on NoC 24
2.3.2 Enhance Throughput Technologies on NoC 25
2.3.3 Reduce Latency Technologies on NoC 27
2.4 Fault-Tolerant Approaches 28
2.4.1 Fault-Tolerant with Circuits 28
2.4.2 Fault-Tolerant with Routing Algorithm 29
Chapter 3 Adaptive Instruction Codec Architecture Design for Network-on-Chip 33
3.1 The Number of Segments and Formats Flit Analysis 35
3.1.1 Effective Number of Segments Analysis 35
3.1.2 Flit Formats of Protocol in AICA with 16-bit 37
3.1.3 Flit Formats of Protocol in AICA with 64-bit 38
3.2 Adaptive Instruction Codec Architecture 44
3.3 Design of AICA with 16-bit 46
3.3.1 Design of AICA Encoder with 16-bit 46
3.3.2 Design of AICA Decoder with 16-bit 49
3.4 Design of AICA with 64-bit 50
3.4.1 Design of AICA Encoder with 64-bit 51
3.4.2 Design of AICA Decoder with 64-bit 54
Chapter 4 Self-Healing Architecture for Network-on-Chip 56
4.1 Self-Healing Architecture with VCs 58
4.1.1 Design of Virtual Channel Fault Detector 59
4.1.2 Design of Virtual Channel Self-Heal 62
4.1.3 VCs Self-Healing Architecture Healing Time Analysis 65
4.2 Self-Healing Architecture with Arbiter 66
4.2.1 Design of Arbiter Fault Detector 67
4.2.2 Design of Arbiter Self-Heal 70
4.2.3 Arbiter Self-Healing Architecture Healing Time Analysis 72
Chapter 5 Stable and Efficient Structure for Network on Chip 74
5.1 Power Consumption Analysis 75
5.2 Performance Analysis 76
Chapter 6 Experimental Results 78
6.1 Experimental Setup 78
6.2 Results of Adaptive Instruction Codec Architecture 79
6.3 Results of Self-Healing Architecture 84
6.3.1 Verification Methods 84
6.3.2 Circuit Diagrams and Measurement Results 85
6.3.3 Self-Healing Time Verification 89
6.4 Comparisons of AICA and Other NoC Architectures 90
6.5 Comparisons of SHA and Unused Fault-Tolerant Architectures 92
6.5.1 Transient Faults Occurred in VCs 93
6.5.2 Transient Faults Occurred in Arbiter 95
6.6 Comparisons of SHA and Fault-Tolerant Architectures 97
6.7 Verification Stable and Efficient Structure 99
6.7.1 Measurement Results 99
6.7.2 Comparisons Performance of AICA_SHA and Other Papers 105
Chapter 7 Conclusions and Future Works 118
7.1 Conclusions 118
7.2 Future Works 119
BIBLIOGRAPHY 121
APPENDIX 131
A. VITA 131
B. PUBLICATIONS 132

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