臺灣博碩士論文加值系統

高速類比數位轉換器和數位類比轉換器是目前高效能系統中不可獲缺的主要電路。高速數位類比轉換器在設計上，需要考慮如何將電路不匹配所造成的靜態和動態的誤差如DNL、INL 和SFDR 等誤差降低，以增加電路的解析度。
本論文設計實現一個12 位元500MHz 的數位類比轉換器，主要著重在SFDR 的設計，在數位類比轉換器電路的實現，切換電流源式是一個很好的實現方法。在編碼方面，由於考量到電路的線性度表現，還有晶片面積的大小，所以採用低位元及高位元不同的編碼；低位元採用二進位權重，高位元採用溫度計編碼。除此之外，為了增進數位類比轉換器的動態效能及提高解析度與元件間的匹配，分別使用了抑制突波的拴鎖器和特殊的佈局，來增加數位類比轉換器的效能。整個電路利用電流源的切換，已達到較高的速度，電流源利用PMOS 來達成，以降低本身電路的flick noise 及substrate 的干擾。同時也考量了在佈局繞線時產生的寄生電容，所造成速度還有信號不同步的效應。這個數位類比轉換器採用TSMC 0.18 μm 1P6M mixedsignal CMOS 製程來實現，整體晶片的核心面積為1.615 mm2，加入PADs之後為2.896 mm2。

Digital-To-Analog converters are essential components of modern applications, such as digital signal synthesis, video signal processing, and both wired and wireless transmitters.For data converters used in communications applications, the integral nonlinearity (INL) and
differential nonlinearity (DNL) are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR).
The major target specification for SFDR of this paper, a 12-bit 500-MSample/s D/A converter, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to
derive maximum benefit from this relatively advanced technology. This architecture is divided into a coarse sub-DAC and a binary-weighted fine sub-DAC. The differential
switches of current sources are controlled by deglitch
latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization. A 12-bit 500-MSample/s current-steering D/A converter integrated in a TSMC 0.18μm CMOS technology is presented. It is based on a current steering doubly segmented 8 + 4 architectureand requires no trimming, no calibration, or dynamic averaging. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch. The measure resultant shows that with the signal frequency of 34.33 MHz at the update rate of 100 MHz, the SFDR is 32 dB. The differential nonlinearity and integral nonlinearity are below 3.3 and 5.4 least significant bits (LSB’s), respectively. The converter consumers a total power of 128 mW and it’s active area is 1.615 mm2.

Abstract (Chinese) I
Abstract (English) II
Acknowledgment IV
Table of Contents V
List of Figures VII
List of Tables X
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Organization 2
Chapter 2. Digital-to-Analog Converter Architecture 3
2.1 Ideal D/A converter 3
2.2 Static Performance of DACs 4
2.3 Dynamic Performance of DACs 7
2.4 Charge Redistribution DAC 9
2.5 R-2R Ladder DAC 11
2.6 Binary Weighted Current-Steering DAC 12
2.7 Thermometer Coded DAC Architecture 14
2.8 Hybrid DAC Architecture 15
2.9 Summary 17
Chapter 3. Nonidealities in Current-Steering DAC 18
3.1 Finite output impedance of current source 19
3.2 Current Source Mismatch 25
3.2.1 Random Error 25
3.2.2 Systematic Error 27
3.3 Nonidealities Due to Switching in the Current Cells 31
3.4 Clock Jitter 33
3.5 Summary 34
Chapter 4. DAC Circuit Design 35
4.1 The Architecture of DAC 35
4.2 Digital Circuits 38
4.2.1 Thermometer decoder 39
4.2.2 High speed latch 40
4.3 Analog Circuits 42
4.3.1 Implementation of Switch Unit Current Cell 43
4.3.2 Reference Current Generation 45
4.4 Layout 47
4.5 Summary 51
Chapter 5. Simulation and Measurement Results 52
5.1 Simulation results 52
5.2 Test Circuits 55
5.3 Measurement Results 57
Chapter 6. Conclusions and Future Work 61
Reference 62

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