臺灣博碩士論文加值系統

過度的電源供應雜訊造成的問題隨著製程技術進步越來越具挑戰。在掃瞄移位時脈邊緣時發生的電源供應雜訊峰值將導致掃瞄失效和良率損失。本論文提出了一個測試時域最佳化的可測試性設計來降低正反器密度，即掃瞄鍊位移時，一個區域內受同一測試時脈所觸發的正反器的最大數目。本技術只調整測試時域與掃瞄鍊的配置。自動測試圖樣產生的演算法和錯誤涵蓋率並未受到影響。在ITC''99中最大的電路b19上的實驗數據顯示，本技術成功的將傳統測試電電路上掃瞄鍊位移時的電源供應雜訊峰值降低了百分之四十九點二，而電路的面積只增加了百分之二。

Excessive power supply noise (PSN) is a more and more challenging problem when the design technology shrinks. The peak power supply noise (PPSN), which occurs at the clock edges of scan shift cycles, causes scan failure and yield loss. This thesis proposes a DfT technique called test clock domain optimization to reduce the PPSN during scan shift cycles by reducing the maximum flip-flop density (MFFD), which refers to the maximum number of flip-flops in triggered by the same test clock during scan shift cycles within a region. The proposed technique only adjusts the test clock domains and the scan chain configuration. The ATPG algorithm is not changed, and the fault coverage is preserved. The experimental data on the largest ITC’99 benchmark circuits b19 shows that the PPSN during the scan shift cycle is reduced 49.2% compared with the traditional technique while the area overhead is only 2%.

摘要 i
Abstract ii
Table of Contents iii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
Section 1.1 Motivation 1
Section 1.2 Proposed Technique 4
Section 1.3 Contributions 7
Section 1.4 Organization 7
Chapter 2 Background 8
Section 2.1 Low Power ATPG and X-filling Techniques 9
Section 2.2 DfT for Low Power Testing 12
Section 2.3 Power Supply Noise 16
Chapter 3 Proposed Technique 28
Section 3.1 Proposed Flow 28
Section 3.2 Test Clock Domain Optimization 30
3.2.1 Initialization 32
3.2.2 Local test clock domain processing 36
3.2.3 Scan chain balancing 41
3.2.4 Scan chain stitching 43
Chapter 4 Experiment Results 45
Chapter 5 Conclusion and Future Work 56
Reference 58

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