臺灣博碩士論文加值系統

本論文探討具有低壓操作電壓特性的蕭特基奈米線電荷捕捉式快閃記憶體其製程製作與量測分析，此元件利用蕭特基源/汲極接面增強熱電子電洞的生成，以提升元件在寫入抹除時的效能。於製程製作上，嘗試使用兩種不同流程方式來進行電荷捕捉式快閃記憶體的奈米線通道製作。實驗過程發現，以乾式蝕刻製作法較能確保製程的穩定性與控制性。於量測分析上，進行不同溫度時電荷捕捉式快閃記憶體的電性量測分析。量測結果顯示，在變溫環境操作下，蕭特基矽奈米線電荷捕捉式快閃記憶體仍保有良好的電性曲線與可靠性表現。

This thesis experimentally explores the process fabrication and measurement characterization of Schottky barrier nanowire charge trapping memories. Two different types of hard-mask lithography were examined to fabricate the gate-all-around nanowire structure. In cell characterization, this work studies the cell reading, programming, and erasing at room and higher temperatures. Reliability characterization in cycling endurance and data retention are also investigated. The results show that the high-temperature Schottky barrier nanowire charge trapping cells preserve good electrical characteristics.

中文摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 緒論 1
1-1. 前言 1
1-2. 非揮發記憶體元件 2
(1) 非揮發記憶體元件特性與種類 2
(2) 浮動閘極記憶體 3
(3) 矽/二氧化矽/氮化矽/二氧化矽/矽（SONOS）記憶體 4
1-3. 金屬矽化物 6
1-4. 論文架構 7
第二章 SONOS記憶體操作機制與可靠度 15
2-1. 通道熱電子寫入 15
2-2. 帶對帶穿隧抹除 16
2-3. 福勒-諾德漢穿隧寫入抹除 17
2-4. 蕭特基能障介紹及操作機制 17
2-5. 操作時間 19
2-6. 耐久度/保持力 19
第三章 元件製作與實驗參數 30
3-1. 元件製作流程 30
3-2. 通道製作與尺寸調變 32
3-3. 源/汲極材料變換與退火參數測試 34
3-4. 摻雜隔離使用與時機 35
第四章 元件電性量測與研究 41
4-1. 製作結果分析 41
(1) 濕式蝕刻調變奈米線 41
(2) 元件讀取 41
(3) 元件抹除 42
(4) 元件切面討論 42
4-2. 元件電性量測 44
(1) 室溫下電性 44
(2) 不同溫度下電性變化 45
(3) 溫度對耐久度/保持力之影響 46
第五章 結論 73
參考文獻 74

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