臺灣博碩士論文加值系統

本論文介紹了一種高精準度和寬的操作頻率範圍的訊號產生器 (Pulse Generator, PG)，其時間解析度為1.96 ps。訊號產生器包括鎖相迴路(Phase Locked Loops, PLL)，邊緣合成器(Edge Combiner, EC)和前端電路(Front End Circuit, FEC)。鎖相迴路為邊緣合成器提供4 GHz的操作頻率,輸入頻率為200 MHz。邊緣合成器利用粗調電路(Coarse Tune Stage, CTS)和細調電路(Fine Tune Stage, FTS)，實現具有寬的操作頻率輸出與可調變的每一個脈波延遲時間。粗調電路使用同步計數器與週期選擇器來實現寬的操作頻率範圍。而細調電路採用MOS電容器組成延遲單元電路，此架構可以實現高的時間解析。因此，延遲元件電路可以使訊號產生器獲得高精度波形。在前端電路的部分可以同時儲存十六個脈波訊號數據，如此訊號產生器可以在4 ns時間內產生十六組脈波訊號，且最小脈波訊號寬度為250 ps。
測試晶片使用TSMC 65nm CMOS製程實現。訊號產生器的核心面積和晶片面積分別為38 × 225 um2和850 × 850 um2。訊號產生器脈波延遲時間範圍為250 ps至64 ns。訊號產生器的功耗在1.2 V時為36 mW。訊號產生器的時間解析度和精準度分別為1.96 ps和±0.3 LSB。

This thesis describes a high accuracy and wide data rate range of pulse generator (PG) with a 1.96 ps time resolution. The PG comprises a phase locked loops (PLL), a edge combiner (EC) and a front end circuit (FEC). The phase locked loop provides 4 GHz operating frequency to an EC. The EC utilizes a coarse tune stage circuit (CTS) and a fine tune stage circuit (FTS) to achieve a wide operating frequency of the event and a modulation of the spacing of each event. The CTS uses a synchronous counter and a cycle detector for a wide operational range. The FTS also adopts MOS Capacitor for delay cell circuit. This scheme can achieve high timing resolution. Thus, the PG can obtain high accuracy waveforms via delay cell circuit. The FEC can store 16 event data at the same time. Thus, this PG can create 16 events at a range of 4 ns, and the is 250 ps.
The test chip was implemented in a TSMC 65 nm CMOS process. The core area and chip area are 38 × 225 um2 and 850 × 850 um2, respectively. The pulse delay time range of PG is from 250 ps to 64 ns. The power consumption of PG is 36 mW at 1.2 V. The time resolution and average accuracy of the PG were measured to be 1.96 ps and ±0.3 LSB, respectively.

摘 要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第1章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章 訊號產生器技術探討 4
2.1 訊號產生器種類簡介 4
2.2 訊號產生器架構探討 5
2.2.1 可調式八通道之信號產生器 [13] 5
2.2.2 應用於測試平台之高精準度任意時序產生器 [14] 6
2.2.3 應用於自動測試機台之時間訊號產生器 [19] 7
2.2.4 內插式數位時間轉換器 [24] 9
2.2.6 訊號產生器架構規格比較 11
2.3 本論文預計規格 12
第3章 訊號產生器架構與邊緣合成器電路 14
3.1 設計概念 14
3.2 訊號產生器架構及操作 14
3.3 邊緣合成器電路與子電路介紹 20
3.3.1 週期選擇器(Cycle Detector) 20
3.3.2 延遲元件(Delay Cell) 22
3.3.4 邊緣產生器與脈衝合成電路(Edge Generator and Pulse Combiner) 26
3.3.5 負載控制器電路(Load circuit) 27
3.3.6 時脈樹電路(Clock tree) 28
3.4 訊號產生器電路模擬 29
第4章 鎖相迴路電路架構與前端電路架構 32
4.1 鎖相迴路電路架構與子電路架構 32
4.1.1 壓控振盪器(VCO) 33
4.1.2 電荷泵電路(Charge Pump) [26] 36
4.1.3 鎖相迴路Matlab參數模擬 40
4.1.4 鎖相迴路電路模擬 42
4.2 前端電路 44
第5章 電路模擬與晶片量測結果 49
5.1 設計流程 49
5.2 佈局前電路模擬 50
5.3 電路佈局 53
5.4 佈局後電路模擬 55
5.5 量測環境設定 60
5.6 規格比較 61
5.7 晶片照相與量測結果 62
第6章 結論與未來研究方向 63
6.1 結論 63
6.2 未來研究方向 64
參考文獻 65

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