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研究生:郭偉政
研究生(外文):Wei-Zheng Guo
論文名稱:非對稱氫化非晶矽薄膜電晶體在不同電壓和定電流應力下的不穩定性
論文名稱(外文):The Instability of Asymmetric α-Si:H TFTs under Different Voltage Stress and Constant Current Stress
指導教授:劉漢文
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:111
中文關鍵詞:非對稱氫化非晶矽薄膜電晶體電壓應力測試定電流應力測試
外文關鍵詞:Asymmetric α-Si:H TFTsVoltage stressConstant current stress
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氫化非晶矽薄膜電晶體,目前已經被廣泛應用在各種電子產品,雖然技術日趨成熟,但隨著新興技術有機發光二極體發展而成為驅動元件,在電流驅動方面存在著許多可靠度的問題。關於非對稱式氫化非晶矽薄膜電晶體,由於非對稱的結構,我們定義通道寬度較長的結構為U型端,通道寬度較短的結構為I型端,而定義I型端為汲極時會有較大的導通電流,以及極低的漏電流,作為定電流的元件時其可靠度仍需探討。

施加電壓應力之非晶矽薄膜電晶體不穩定性:

閘極電壓愈高,能打斷愈多在通道a-Si:H與閘極絕緣層SiNx 接面的Si-H鍵,進而產生懸浮鍵,當汲極加入直流電壓做應力測試,閘極與汲極間的電位差減小,產生的缺陷也減少。在做交流訊號應力測試時,加在閘極交流訊號頻率高低,對氫化非晶矽薄膜電晶體特性衰退並無相關性,因為交流訊號下,通道內電子堆積的速度比閘極所給的交流訊號快很多。而在一個週期時間的交流訊號內,只有正電壓時間能有效產生缺陷,因此交流訊號對薄膜電晶體的影響相對比直流偏壓小。非對稱式氫化非晶矽薄膜電晶體,因為汲極與源極圖案不同,兩端在受到外加應力後,U型端的通道寬度所產生的缺陷數量比I型端的多,因此選用U型端作為電子輸出端,非對稱式氫化非晶矽薄膜電晶體會有較嚴重的退化現象。

施加定電流應力之非晶矽薄膜電晶體不穩定性:

在1µA定電流應力測試下,對稱式氫化非晶矽薄膜電晶體操作在線性區應力測試比操作在飽和區有較嚴重的退化現象,其原因為線性區下,電子在通道內能有效撞擊汲極端產生缺陷,而在飽和區下,在閘極絕緣層與矽的接面的缺陷因為閘極與汲極間產生空乏區,故沒產生缺陷,而非對稱式氫化非晶矽薄膜電晶體也有相似的情況。在線性區應力測試下,由U型端提供定電流(Is),有較大的退化現象,其原因為等量的電子流撞擊U型端會有較多位置的Si-H鍵可以被打斷產生缺陷。我們也探討了非對稱式氫化非晶矽薄膜電晶體在線性區下10µA與1.3µA之定電流在相同閘極電壓下,定電流較小者有較大的退化現象的原因。在不同閘極電壓與不同定電流應力下,可以藉由觀察電晶體各端點之電壓,參照定電壓應力測試下之不穩定性機制,來探討定電流退化機制,有助於定電流應力下之非晶矽薄膜電晶體不穩定性機制的了解。
The hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) were important electronic devices in many electronic products. The a-Si:H TFT technology in active-matrix liquid-crystal displays (AM-LCD) was applied to new products recent years, the active-matrix organic light emitting displays (AM-OLED). We investigated the asymmetric TFT electrical characteristics under different voltage stress and constant current stress because TFTs would be used as current driver.
The instability of voltage stress:
We made the experiments about DC stress and AC stress. The gate bias was larger, the more degradation in TFT electrical characteristics. Because larger gate bias could induce more electrons, the electrons broke the weak bond, Si-H, at the interface between a-Si and the gate insulator, and induced Si dangling bond defect. Based on this model we add the stressed bias on drain electrode to reduce the voltage between gate and drain electrodes, and the degradation of the TFTs electrical characteristics would become smaller. In AC stress, the bias stress experiment has the same result. But the degradation of AC stress showed no frequency dependence. Because the electrons would rapidly accumulate in the channel, the AC signal was not fast enough to react. Because there were different patterns of drain electrode between and source electrode in the asymmetric TFTs, the U type terminal, which has large channel width, could induce more defects. When U type terminal provided electrons, the electric characters of asymmetric TFTs had larger degradation.
The instability of constant current stress:
The symmetric TFT under 1µA constant current stress, the degradation of TFT operated in linear region was serious than that operated in saturation region. The electrons would break the Si-H bond at the interface between a-Si:H and the gate insulator when TFT operated in linear region, however, the depletion region near drain terminal deduced the electrons to impact the Si-H bond, therefore, it led to the result. We investigated that 1.3µA constant current stress had larger degradation than 10µA on electrical characteristics under the same gate bias in linear region. For the asymmetric TFT, we would explain the degradation mechanism of the constant current stress baseon the DC stress model.
致謝 i
中文摘要 ii
Abstract iii
目次 iv
表目次 vi
圖目次 vii
第一章 簡介 1
1.1 背景 1
1.2 研究動機 3
1.3 文獻探討 4
1.4 論文架構 7
第二章 基本原理介紹 8
2.1 液晶顯示器工作原理 8
2.2 有機發光二極體 10
2.3 氫化非晶矽薄膜特性 12
2.4 非晶矽薄膜電晶體 13
2.5 薄膜電晶體之各種電性參數萃取 15
2.5.1 載子移動率(mobility, μFE)和轉導(Gm)之定義 15
2.5.2 臨界電壓(Vth)之定義 16
2.5.3 導通電流(Ion)與漏電流(Ioff)之定義 16
第三章 元件介紹與實驗流程 17
3.1 元件結構 17
3.2 量測系統介紹 22
3.3 量測方法及流程 23
3.3.1 直流定電壓下之電性不穩性測試 23
3.3.2 交流訊號下之電性不穩性測試 25
3.3.3 定電流下之電性不穩性測試 27
第四章 結果與討論 29
4.1 直流定電壓下之電性不穩性測試 29
4.1.1 對稱式TFT閘極直流偏壓應力測試 29
4.1.2 對稱式TFT閘極直流偏壓下加入汲極直流偏壓應力測試 32
4.1.3 非對稱式TFT閘極直流偏壓應力測試 36
4.1.4 非對稱式TFT閘極直流偏壓下加入汲極直流偏壓應力測試 40
4.1.5 非對稱TFT閘極直流偏壓下加入源極直流偏壓應力測試 43
4.1.6 直流偏壓測試後的飽和區量測 46
4.2 交流訊號下之電性不穩性測試 49
4.2.1 對稱式TFT閘極交流訊號做應力測試 49
4.2.2 非對稱式TFT閘極交流訊號應力測試 52
4.2.3 非對稱TFT閘極交流訊號下加入汲極直流偏壓應力測試 55
4.2.4 非對稱TFT閘極交流訊號下加入源極直流偏壓應力測試 58
4.3 定電流下之電性不穩性測試 64
4.3.1 對稱式TFT定電流下操作在飽和區與線性區 64
4.3.2 非對稱式TFT不同操作區下汲極定電流1.3µA應力測試 70
4.3.3 非對稱式TFT不同操作區下源極定電流1.3µA應力測試 74
4.3.4 非對稱式TFT不同方向定電流1.3µA應力測試比較 78
4.3.5 非對稱式TFT不同操作區下汲極定電流10µA應力測試 81
4.3.6 非對稱式TFT不同操作區下源極定電流10µA應力測試 85
4.3.7 非對稱式TFT不同方向定電流10µA應力測試之比較 89
4.3.8 非對稱TFT在線性區應力測試下相同電流方向不同定電流之比較 92
4.3.9 非對稱TFT在飽和區應力測試下相同電流方向不同定電流之比較 97
4.3.10 定電流應力測試後的飽和區量測 100
第五章 結論 106
5.1 電壓應力之不穩定性 106
5.2 定電流應力之不穩定性 107
參考文獻 109
[1] T. Takahashi, T. Takenobu, J. Takeya, and Y. Iwasa, “Ambipolar Light-Emitting Transistors of a Tetracene Single Crystal,” Appl. Phys. Lett. 88, 033505, 2006.
[2] 施敏 原著,黃調元 譯,半導體元件物理與製作技術,國立交通大學出版社, 2003.
[3] Karim S. Karim, Arokia Nathan, Michael Hack, and William I. Milne, “Drain-Bias Dependence of Threshold Voltage Stability of Amorphous Silicon TFTs, ”IEEE ELECTRON DEVICE LETTERS, VOL. 25,pp. 225-233, NO. 4, 2004.
[4] M.J.Powell, C. van Berkel, I.D. French, and D. H. Hicholls, “Bias Dependence of Instability Mechanisms in Amorphous Silicon Thin Film Transistors,” Appl. Phys. Lett.51, pp. 1242-1244, 1987.
[5] H. Gleskova and S. Wagner, “DC-Gate-Bias Stressing of a-Si:H TFTs Fabricated at 150 ◦C on Polyimide foil,” IEEE Trans. Electron Devices, VOL. 48,no. 8, pp. 1667–1671, 2001.
[6] Chun-Yao Huang, Jun-Wei Tsai, Teh-Hung Teng, Cheng-Jer Yang and Huang-Chung Cheng , “Turnaround Phenomenon of Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Negative Bias Stress,” Jpn. J. Appl. Phys. VOL.39,pp.5763-5766, 2000.
[7] M.J. Powell, C. van Berkel, and A.R. Franklin, “Defect Pool in Amorphous-Silicon Thin Film Transistors,” Physical Review B (Condensed Matter), Volume 45, Issue 8, pp.4160-4170, 1992.
[8] B. Iniguez, L. Wang, T. A. Fjeldly M.S. Shur, and H. Slade, “Thermal, Self-Heating and Kink Effects in a-Si:H Thin Film Transistors,” IEDM Tech. Dig., IEEE Catalog no. 98CH36712, pp. 32.7.1–32.7.4, 1998.
[9] Huang-Chung Cheng, Chun-Yao Huang, Jing-Wei Lin and Jerry Ji-Ho Kung, “The Reliability of Amorphous Silicon Thin Film Transistors for LCD under DC and AC Stresses,” Solid-State and Integrated Circuit Technology, pp.834-837, 1998.
[10] S. C. Dean and M.J. Powell, “Field-Effect Conductance in Amorphous Silicon Thin-Film Transistors with A Defect Pool Density of States,” J. Appl. Phys., VOL.74, no.11, pp.6655-6666, 1993.
[11] Rahul Shringarpure, Sameer Venugopal, Lawrence T. Clark, David R. Allee, Edward Bawolek, “Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs, ” IEEE ELECTRON DEVICE LETTERS, VOL. 29, pp. 93-95, NO. 1, 2008
[12] Alex Kuo, Tae Kyung Won, and Jerzy Kanicki, “Advanced Amorphous Silicon Thin-Film Transistors for AM-OLEDs: Electrical Performance and Stability,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, pp. 1621-1629, NO. 7, 2008.
[13] Shah M. Jahinuzzaman, Afrin Sultana, Kapil Sakariya, Peyman Servati, and Arokia Nathan, “Threshold Voltage Instability of Amorphous Silicon Thin-Film Transistors under Constant Current Stress,” Appl. Phys. Lett.87, 023502, 2005.
[14] Ya Hsiang Tai, Ming-Hsien Tsai, and Shih-Che Huang, “The Linear Combination Model for the Degradation of Amorphous Silicon Thin Film Transistors under Drain AC Stress,” Japanese Journal of Applied Physic Vol. 47, No. 8, pp. 6228–6235, 2008.
[15] Hojin Lee, Juhn-Suk Yoo, Chang-Dong Kim, In-Jae Chung, and Jerzy Kanicki, “Asymmetric Electrical Properties of Corbino a-Si:H TFT and Concepts of Its Application to Flat Panel Displays,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, pp. 654-662, NO.4, 2007.
[16] 戴亞翔, TFT-LCD 面板的驅動與設計, 五南圖書出版, 2006.
[17] 顧鴻壽, 光電液晶平面顯示器技術基礎及應用, 新文京出版社, 2004.
[18] 陳建銘, 液晶顯示器技術入門,全華科技出版社, 2005.
[19] Chih-Lung Lin, “A Novel LTPS-TFT Pixel Circuit Compensating for TFT Threshold-Voltage Shift and OLED Degradation for AMOLED, ”IEEE Electron Device Letters, VOL.28, pp. 129-131, 2007.
[20] 生活科技教育月刊二○○四年三十七卷第三期pp.119-126.
[21] 液晶顯示器技術手冊,紀國鐘教授、鄭晃忠教授主編,台灣電子材料與元件協會出版,2002.
[22] Jun-Wei Tsai, Chun-Yao Huang, Ya-Hsiang Tai, and Huang-Chung Cheng, “Reducing Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors by Hydrogenating the Gate Nitride Prior to Amorphous Silicon Deposition,” Appl. Phys. Lett.71 pp. 1237, 1997.
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