臺灣博碩士論文加值系統

2.5D製程整合使得晶片與晶片之間的資料傳遞就像是在晶片內部的導線上傳遞，因為矽基板(interposer)可以使晶片對晶片的資料溝通變得更快速且擁有更低的功耗。本篇論文提出並設計出一個矽基板上匯流排(on-interposer bus)，稱作μ-SPI(serial peripheral interface)，此匯流排架構可以提供2.5D異質整合系統低功耗訊號傳遞。

μ-SPI的協定架構是利用階層式封包技術來設計，而此架構是建立在傳統SPI之物理層基礎上。在μ-SPI中，資料的寬度可從一個至八個位元；此外，為了要降低封包標頭(packet header)的長度，我們利用階層式封包技術將標頭分為兩層，第一層的標頭長度是固定的，可以用來表示此封包的功能；第二層標頭的長度是可變的，可以用來提供大範圍的資料長度指示、多個從設備的選擇以及不同的資料地址長度。除此之外，我們提出一個虛擬多重主設備(pseudo multi-master)來取代傳統多重主設備的仲裁電路(arbitration circuits)，透過單一主設備的控制權傳輸，可用來設定在主從模組中的主從標誌(MS_Flag)；因此，在同一時間只會有一個主設備存在。此外，我們將此論文所提出的μ-SPI應用在一個2.5D異質整合之生物感測微系統上，當矽基板上的電壓及操作頻率分別為1.8V及100 KHz時，所提出的矽基板上匯流排之平均功耗僅23.2 µW。

2.5D integration allow to inter-chip communication between multiple chips with intra-chip interconnects. The interposer provides fast and low power chip-to-chip communication. In this thesis, an on-interposer bus (μ-SPI, serial peripheral interface) is presented for providing low power data communication in 2.5D heterogeneous integrations.

The protocol of μ-SPI is designed by a hierarchical packetization technique based on the physical layer of SPI. The data width of μ-SPI is from 1-bit to 8-bit. To reduce the overhead of the header, the header of a packet is divided into two levels by the hierarchical packetization technique. The length of 1st level header is fixed for indicating the functionality of this packet. Based on the information of 1st level header, the 2nd level header is variable for providing wide range of the burst length, broadcasting selection and variable address. Moreover, a pseudo multi-master is proposed to replace the arbitration circuits via master passing. Only 1 master can exist by controlling MS_Flag in master/slave modules. The proposedμ-SPI is utilized in a 2.5D heterogeneously integrated bio-sensing microsystem. The average power of this on-interposer bus is only 23.2 µW at 1.8V and 100 KHz.

Content
Chapter 1 Introduction 1
1.1 Motivation 2
1.2 Research Goals and Major Contributions 3
1.3 Thesis Organization 5
Chapter 2 Overview of 2.5D/3D Integrations 6
2.1 Benefits of 2.5D/3D Integrations 6
2.2 Categories of 3D Integration Technology 10
2.3 TSV 3D Integrations 14
2.3.1 Stacking Approach 15
2.3.2 Stacking Orientation 15
2.3.3 Bonding Methods 17
2.3.4 TSV Formation 18
2.3.5 Categories of TSV Scheme 19
2.4 TSV 2.5D Integration 20
2.4.1 Process Characteristics of 2.5D Integration 21
2.4.2 TSV Technology for 2.5D Integration 25
2.4.3 Wafer-Level Package for 2.5D Integration 26
2.4.4 2.5D Design Methodology 28
Chapter 3 Analysis and Modeling of Interposer in 2.5D Integration 30
3.1 Physical and Electrical Modeling of TSV 30
3.2 Physical and Electrical Modeling of Interposer 31
3.2.1 Coupled Lines on Interposer 32
3.2.2 ASE Equivalent Electric Model 35
3.3 Timing Analysis of On-Interposer Bus 36
3.4 Power Analysis of On-Interposer Bus 41
3.5 Timing &; Power Models of On-Interposer Bus 47
3.6 Summary 50
Chapter 4 μ-SPI: Low Power On-Interposer Bus 51
4.1 Inter-Chip Communication in 2.5D Integration 51
4.2 Features of Synchronous Protocols: SPI &; I2C 52
4.2.1 SPI Overview 53
4.2.2 I2C Overview 56
4.2.3 SPI vs. I2C 59
4.3 μ-SPI: A Low Power On-Interposer Bus 61
4.3.1 Protocol of μ-SPI 61
4.3.2 Parallel Interface &; Shared Slave Selection Pin 62
4.3.3 Hierarchical Header for μ-SPI 63
4.3.4 Pseudo Multi-Master 69
4.3.5 Receive-Controlled Acknowledgement 71
4.4 Summary 72
Chapter 5 μ-SPI for 2.5D Heterogeneously Integrated Neural-Sensing Microsystems 74
5.1 Abstraction Layers of μ-SPI 74
5.1.1 Physical Layer 74
5.1.2 Data-Link Layer 78
5.1.3 Transport Layer 79
5.2 Slave Design for μ-SPI 80
5.3 Master-Slave Design for μ-SPI 84
5.4 Experimental Results for μ-SPI 86
5.5 μ-SPI for 2.5D Heterogeneously Integrated Neural-Sensing Microsystems 93
5.6 Summary 100
Chapter 6 Conclusions and Future Works 102
6.1 Conclusions 102
6.2 Future Works 103
References 105

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Chapter 6
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