臺灣博碩士論文加值系統

本論文主要目的為探討奈米積體電路製程中之摻碳氧化矽 (SiOC:H)低介電常數薄膜及利用紫外線處理及熱處理對其薄膜性質的影響。以及探討電化學機械拋光處理在積體電路製程上的應用及其性質的研究，第一部分，利用電漿輔助化學氣相沈積法，將結構形成物(matrix)的前驅物二乙氧基甲基矽烷(DEMS)與碳氫化合物構成的成孔劑(porogen)物質C10H16(a-Terpinene)共沉積為含有成孔劑(porogen)的摻碳氧化矽(SiOC:H)薄膜，主要研究低介電薄膜經不同紫外光處理時間處理後，觀察其薄膜特性的變化。實驗結果顯示，擁有摻雜porogen的薄膜會因為紫外光處理後將porogen移除產生孔洞，造成較低的介電常數且擁有較佳的機械特性和電特性。
第二部分，探究銅電化學機械研磨(ECMP)形成機制在奈米半導體積體電路製程之研究。在此研究中，利用高解析穿透式電子顯微鏡(HRTEM)與X射線光電子能譜分析儀(XPS)探討薄膜頓化層微結構及表面成長機制，並利用電化學阻抗儀(EIS)與Potentiodynamic 極化曲線進行電化學之電性研究。另一方面探討經電化學機械研磨的銅平坦化效能(PE)之變化，及其在奈米半導體積體電路製程之研究。

The objective of this study is to investigate a suitable low dielectric material (low-k)and copper (Cu)electrochemical mechanical planarization (ECMP) mechanism for the application of the nanometer integrated circuits.
The main focus of this dissertation can be divided into two parts. First, the film is deposited from the decomposition of two precursors in the plasma. Both matrix (DEMS) and precursors (C10H16) are transformed into species that eventually lead to the formation of a hybrid film composed of an organ silicate-based matrix enclosing organic inclusions.
Then, during the UV curing and thermal treatment, the organic phase, mostly consisting of the porogen molecule fragment, is removed. As the result, the film become porous and has ultra low-k properties and has better mechanical and electric properties by UV curing than thermal annealing.
Second, we have investigated the microstructures and growth mechanism of passive film on the Cu surface by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy. The electrochemical properties of the samples were investigated by electrochemical impedance spectroscopy (EIS) and potentiodynamic polarization curve. In addition, we have evaluated the planarization efficiency (PE) after ECMP processing in the in the semiconductor integrated circuits.

目錄
中文摘要 ............................................................................................................................. I
Abstract ............................................................................................................................... II
致謝 .................................................................................................................................. III
目錄 .................................................................................................................................. IV
圖目錄 ............................................................................................................................... VI
表目錄 ............................................................................................................................... XI
第一章 緒論 ....................................................................................................................... 1
1-1 研究背景 ................................................................................................................... 1
1-2 銅導線 ( Cu interconnect ) 與 低介電材料( Low-k material ) ................................ 5
1-3 研究目的 ................................................................................................................... 6
第二章 理論基礎 ................................................................................................................ 9
2-1 積體電路發展簡史[14] .............................................................................................. 9
2-2 介電材料 (Dielectric Materials) ............................................................................... 9
2-2-1 材料的極性與極化 (Polarizability and Polarization) ....................................... 14
2-2-2 材料的介電行為 ............................................................................................... 16
2-3 低介電常數材料 (Low Dielectric Materials，Low-k) ............................................ 21
2-3-1 介電材料對元件的重要影響 ........................................................................... 21
2-3-2 低介電常數材料的選擇 ................................................................................... 22
2-3-3 低介電材料的種類 ........................................................................................... 42
2-3-4 低介電常數材料的要求 ................................................................................... 43
2-4 化學氣相沉積法 (Chemical Vapor Deposition，CVD) ......................................... 51
2-5 鑲嵌結構 ( Damascene Process )[50] ...................................................................... 55
2-6 平坦化製程之研磨機制 ........................................................................................... 59
第三章 實驗方法與步驟 .................................................................................................. 63
V
3-1 實驗流程 ................................................................................................................. 63
3-2 介電薄膜沉積 ......................................................................................................... 64
3-2-1 薄膜沉積設備 ................................................................................................... 64
3-2-2 反應前趨物與沉積條件 ................................................................................... 64
3-2-3 ECMP 試片製備 ................................................................................................ 72
3-3 分析儀器 ................................................................................................................. 74
3-3-1 多波長光學橢圓儀 (Spectroscopic Ellipsometery) .......................................... 74
3-3-2 傅利葉轉換紅外線光譜儀 (Fourier Transform Infrared Spectrometer，FTIR) 77
3-3-3 電容–電壓與電流–電壓量測分析儀 (C–V and I–V Analyzer) ....................... 81
3-3-4 電化學量測 ....................................................................................................... 84
3-3-5 電化學阻抗儀(EIS) ........................................................................................... 84
3-3-6 能量分散光譜儀（Energy-dispersive Spectrometer, EDS） ............................ 85
第四章 結果與討論 .......................................................................................................... 86
4-1 碳摻雜氧化矽薄膜 ................................................................................................. 86
4-2 紫外光處理對低介電材料的影響 ........................................................................ 103
4-3 介電阻障層 ........................................................................................................... 118
4-4 銅電化學拋光處理及化學機械硏磨 .................................................................... 129
第五章 結論 ................................................................................................................... 150
參 考 文 獻 ................................................................................................................... 152

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