臺灣博碩士論文加值系統

碳化矽因為具有寬能隙以及高熱傳導係數，適合用來製作高功率元件。但是碳化矽的金氧半場效電晶體(MOSFET)的製作仍有很大的改善空間，如通道載子移動率的提升是個很重要的課題。氧化層與碳化矽基板之間的高介面能態密度(大於1012 cm-2)是造成低載子移動率的主因，且既有的閘極氧化層製程都需要1300以上的高溫氧化及退火，才能得到可接受的閘極氧化層。本論文研究利用低熱預算製程來降低介面能態密度，比較多種低熱預算製程對各項電性參數包含介面能態密度、介電層崩潰電場分布的影響，並探討不同的製程條件與介面能態密度的關係。
我們利用直接低溫(1050 ℃)濕氧氧化的條件當作本論文介面能態密度的參考上限，理論上氧化厚度越薄介面能態密度越小，研究發現濕氧30分鐘介面能態密度就達到飽和，原因是溫度不夠高使得一氧化碳(CO)不容易擴散到氧化層表面。高溫(1300 ℃)一氧化二氮直接氧化的條件做為本論文介面能態密度的參考目標。在距離導帶(conduction band) 0.4 eV的介面能態密度，低溫濕氧大約是5x1011 cm-2eV-1，而高溫一氧化二氮為4.67x1010 cm-2eV-1，有將近十倍的差距。。
一氧化二氮(N2O)或阿摩尼亞(NH3)低溫(1100 ℃)爐管退火可以些微改善介面能態密度，兩種製程的疊加可以更進一步改善介面能態密度，在距離導帶0.4 eV處的數值為2.92 x1011 cm-2eV-1。在崩潰電場方面，一氧化二氮退火可以增加崩潰電場但仍有較寬的電場分佈，可見一氧化二氮退火可以改善氧化層的品質，但是對於碳化矽基板不平整所造成的局部電場加強導致的提早崩潰，作用不大。增加一層低壓化學氣相沈積的氮化矽層可以明顯提高崩潰電場並改善崩潰電場分佈，推測是因為氮化矽和二氧化矽層的缺陷不容易疊對，故不易形成導通路徑。
氨氣電漿處理可以大幅改善介面能態密度，但是在電漿處理過後會產生0.5-1 V的平帶電壓的偏移，此負電荷的產生機制，尚不明瞭。電漿功率在150瓦跟200瓦有相同的改善趨勢，五分鐘比兩分鐘來的好，十分鐘即達到飽和。200瓦介面能態密度略高於150瓦，可能是主因是功率太高產生額外的缺陷，而100瓦功率不夠高即使時間加長到十五分鐘還是不如150瓦十分鐘的效果好。以化學氣相沈積製程製作介電層堆疊的方法有最低的熱預算，但是介面能態密度高於直接濕氧的條件，所以需要進一步退火處理。崩潰電場分佈很廣，推測原因是第一層的氧化層的品質不好，其中機制尚待探討。最後，我們以高溫量測萃取深能帶的介面能態密度，發現各種介面能態密度改善製程的有效範圍大約是在靠近導帶0.2-0.8 eV區間，對於1 eV以下的介面能態無明顯改善效果。
二次離子質譜儀縱深分析顯示高溫(1300 ℃)一氧化二氮直接氧化的試片，在二氧化矽/碳化矽介面有氮堆積現象，其它試片則無。推測氮在二氧化矽中不易擴散，如果先成長純二氧化矽，再進行氮處理，如果製程溫度不夠高，氮無法到達二氧化矽/碳化矽介面，故介面能態的改善效果不佳。
在所有低預算製程改善中，適當的氨氣電漿處理能達到較低的介面能態密度，其數值大約是1.37 x1011 cm-2eV-1，但是介面能態密度還是高出本論文最低參考值三倍(高溫一氧化二氮氧化)，且氨氣電漿處理的熱預算太低，只有氫可鈍化介面能態，推測氫鈍化只對淺能帶的介面能態有效，對0.5 eV以上的介面能態無效。如果要達到更低值，在新製程開發出來之前，高熱預算的製程還是的無法避免。

Silicon carbide (SiC) is suitable for fabricating high power semiconductor devices because of its wide band-gap and high thermal conductivity. Unfortunately, low channel mobility occurs on the 4H-SiC MOSFETs due to the high SiO2/SiC interface state density. How to reduce interface state density is an important issue. In this thesis,
several low thermal budget processes to reduce interface state density are evaluated. Electrical parameters including interface state density and breakdown field distribution are analyzed. The effect of process conditions on interface state density is also discussed.
The low temperature (1050 ℃) wet oxidation sample set provides the higher bound reference of the interface state density (Dit) in this thesis. It is expected that the shorter oxidation time would result in lower interface state density. However, it is observed that lots of carbon clusters saturate on the 0.5 hr wet oxidation sample. It is suspected that the oxidation temperature is not high enough for the diffusion of CO. The interface state density of the wet oxidation sample set is around 5x1011 cm-2eV-1 at Ec-E = 0.4 eV. High temperature (1300 ℃) N2O oxidation sample sets the lower bound reference of Dit. The Dit value of this sample is 4.67x1010 cm-2eV-1 and is 10 times lower than that of the wet oxidation samples.
Low temperature (1100 ℃) post-oxidation annealing, with the N2O annealing or NH3 annealing, can improve the interface quality separately. The N2O annealing and NH3 annealing have superimposed effect the Dit can be improved to 2.92 x1011 cm-2eV-1 at Ec-E = 0.4 eV. N2O annealing can improve breakdown field but the breakdown field variation is still large. These results indicate that N2O annealing can improved oxide quality but the early breakdown due to the rough SiC surface cannot be changed. Samples with Si3N4 capping have tight breakdown field distribution because weak spots in the wet oxide do not coincide with the weak spot in the nitride layer so that early breakdown could be suppressed because current path is hard to form.
NH3 plasma treatment can improve Dit effectively but a 0.5~1 V positive shift of flat-band voltage compared to wet oxidation sample is observed on all of the plasma treated samples. The trends of interface improvement by plasma treatment at 150 W and 200 W are similar. The interface state density decreases as the plasma treatment time increases from 2 minutes to 5 minutes and gradually saturates as the plasma treatment time increases to 10 minutes. At the same plasma treatment time, 200 W results in slightly higher interface state density than 150 W. It is suspected that higher plasma energy produces additional interface defects due to the stronger radiation. The 100 W 15 min sample has higher Dit than 150 W 10 min. It is thus concluded that 150 W 10 minutes is the optimized condition. Lower energy cannot passivate interface states effectively even if 15 min treatment.
Dielectric stacks sample has the lowest thermal budget. However, it has the highest interface state density among all samples. Post-deposition annealing is required. Dielectric stacks sample exhibits wide breakdown field variation. It is suspected that the quality of the bottom PECVD oxide is too poor. Finally, to extract deep level interface states, high temperature measurement would be required. It is observed that the Dit improvement occurs only in the range of Ec-E = 0.2-0.8 eV. As Ec-E > 1 eV, there is no Dit improvement on all the samples.
Secondary ion mass spectroscopic analysis shows nitrogen pile-up at the SiO2/SiC interface on the sample HT. This phenomenon is not observed on the other samples. It is suspected that the diffusion of nitrogen radicals in SiO2 is slow. If nitrogen incorporation is processed after SiO2 growth, there are not sufficient nitrogen radicals can reach the interface at low thermal budget processes.
Although suitable NH3 plasma treatment achieves the lowest interface state density among these low thermal budget samples, Dit = 1.37x1011 cm-2eV-1, this value is still 3 times higher than the lowest bound reference. Furthermore, the thermal budget of the plasma treatment is too low. Only hydrogen can passivate the interface states. It is suspected that hydrogen can only passivate shallow level interface states and does not affect the interface states deeper than 0.5 eV. To achieve very low interface state density, novel low thermal budget processes must be developed. Otherwise high thermal budget process is still unavoidable.

Chapter 1 Introduction 1
1-1 History of Semiconductor Power Devices 1
1-2 Overview of Wide Band-gap Materials 3
1-3 Silicon Carbide (SiC) Crystals 4
1-4 Oxidation Issues of SiC 5
1-5 Motivation 8
1-6 Thesis Organization 9
Chapter 2 Experiments 15
2-1 MIS Capacitor Fabrication 15
2-2 Electrical Characterization 17
2-3 Material Analysis 21
Chapter 3 Results and Discussion 26
3-1 1050 ℃ Wet Oxidation 26
3-2 High Temperature Oxidation 29
3-3 N2O and NH3 Post-Oxidation Annealing 30
3-4 NH3 Plasma Treatment 32
3-5 Dielectric Stacks 33
3-6 High Temperature Measurement 34
3-7 Summary of Interface State Density Characteristic 37
Chapter 4 Conclusion and Future Works 68
4-1 Conclusion 68
4-2 Future Works 70
References 72
Author’s Biography 76

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