臺灣博碩士論文加值系統

本文中探討了在90奈米CMOS製程之下，口袋埋置效應對於RTN帶來的衝擊。我們的研究成果顯示了由於沿著通道方向不均勻的門檻電壓分布，口袋埋置構造將會造成雜訊特性的劣化。文中將會提出一個簡單的兩區模型來討論口袋埋置效應，並藉著對SONOS使用熱電子寫入的方式來確定口袋埋置結構確實會對RTN造成影響
本文中另外也探討了通道長度效應和pMOS之間的關係，當元件尺件縮小，越小的通道長度將會因為口袋埋置濃度造成更嚴重的雜訊行為劣化。不同通道長度和不同口袋埋置濃度對元件造成的影響將會利用模擬的方式驗證。

Chinese Abstract i
English Abstract ii
Acknowledgements iii
Contents iv
Figure Captions vi
Chapter 1 Introduction 1
Chapter 2 Fundamental of Random Telegraph Noise 3
2.1 Introduction 3
2.2 Random Telegraph Noise Theory 3
2.2.1 Gate Voltage dependence of RTNs 3
2.2.2 Electron Capture and Emission in RTNs 4
2.3 Measurement Setup of RTN 6
Chapter 3 Investigation and Characterization of Channel Non-uniformity induced RTN 12
3.1 Introduction 12
3.2 Two-Region Model Theory 12
3.3 Experiment and Statistic of RTN induced current fluctuation on sub-100 nm MOSFETs 13
3.4 Verification of Non-uniformity Threshold Voltage Effect by SONOS programming 15
Chapter 4 Investigation of Channel Non-uniformity Effect by Device Simulation 30
4.1 Introduction 30
4.2 Simulation of channel non–uniformity on pocket devices 30 iv
Chapter 5 Conclusion 38
References 39

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