臺灣博碩士論文加值系統

　　本論文是一個工作於UHF頻段的15-bit被動式RFID Tag，主要是應用於RFID室內定位系統。系統運作於兩組頻率：使用2.45GHz的連續波做為電路充電及提供Tag反散射用；另一組使用925MHz或866.4MHz的頻率，傳送含資料調變的訊號給Tag判斷及編碼。在應用上，為了使定位系統使用在更大的空間中，本論文的重點著重於極低讀取功率的RFID Tag。在電路架構中省去了較耗電的穩壓器及震盪器，做出最低讀取功率為-23dBm的RFID Tag。由於PIE symbol為self-timing的訊號，本論文提出了新的解碼方式，將PIE symbol解碼為binary訊號。本論文利用台積電TSMC 0.18μm 1P6M CMOS製程來實現，由Full-Custom設計流程來完成。

　　This thesis presents an UHF passive radio-frequency-identification (RFID) tag chip. This tag is applicated in RFID indoor localization system. The system operates at dual bands: the 2.45GHz continue wave for charge the tag and backscattering the RF data to the Reader; the other band, 925MHz or 866.4MHz for receiving and decoding the modulated signal. For the indoor localization system, this thesis designs a low power consumption RFID Tag. We remove the regulator and the oscillator, which are known to consume a large amount of power. The lowest RF power that our Tag can work is -23dBm. Since the PIE symbol is self-timing, this thesis presents a new method to decode PIE symbols to binary codes. The proposed RFID tag is designd in TSMC 0.18μm 1P6M CMOS process in Full-Custom design flow.

摘要 I
Abstract II
目錄 IV
圖目錄 VII
表目錄 XI
第一章、緒論 1
1-1 簡介與背景 1
1-2 RFID的特色 2
1-3 研究動機與目的 4
1-4 使用工具與模擬軟體 5
1-5 論文架構 6
第二章、RFID系統介紹 7
2-1 RFID系統使用頻段的選擇 7
2-2 RFID系統於空間定位的應用 8
2-3 RFID系統的編碼與調變 10
2-3.1 ASK、FSK及PSK 10
2-3.2 OOK 12
2-3.3 PIE (Pulse-Interval Encoding) 12
2-3.4 FM0 14
第三章、RFID Tag電路設計 16
3-1 Tag電路架構 16
3-2 Charge Pump, Limiter, and Power-On Reset Circuit 17
3-2.1 Dickson rectifier 18
3-2.2 Charge Pump 19
3-2.3 Limiter and Power-On Reset Circuit 20
3-3 Demodulator 21
3-3.1 Envelope detector 21
3-3.2 PIE-to-binary Decoder 23
3-4 Baseband Processing Unit (BPU) 25
3-5 FM0 Encoder 28
3-6 Back-Scatter Circuit 30
第四章、模擬與量測結果 31
4-1 Sub-circuit Simulation Results— Charge Pump, Limiter, and Power-On Reset Circuit 31
4-1.1 The Lowest Input Power in Different Corners 32
4-1.2 The Medium Input Power in Different Corners 33
4-1.3 The Highest Input Power in Different Corners 34
4-2 Whole Chip Simulation Results— Analog circuits ? Post-Simulation Digital circuits ? Pre-Simulation 35
4-2.1 The Lowest Input Power in Different Corners 35
4-2.2 The Medium Input Power in Different Corners 39
4-2.3 The Highest Input Power in Different Corners 41
4-3 Whole Chip Simulation Results— Analog circuits ? Pre-Simulation Digital circuits ? Post-Simulation 44
4-3.1 The Lowest Input Power in Different Corners 44
4-3.2 The Medium Input Power in Different Corners 47
4-3.3 The Highest Input Power in Different Corner 49
4-4 Back-scatter電路模擬結果 51
4-5 下線實作與量測結果 52
4-5.1 設計流程 52
4-5.2 晶片佈局腳位介紹及PCB版呈現 53
4-5.3 PCB電路板製做 55
4-5.4 量測環境 56
4-5.5 量測結果 57
4-6 與其他文獻比較 59
第五章、結論與未來展望 61
5-1 結論 61
5-2 未來展望 61
參考文獻 64

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