臺灣博碩士論文加值系統

在主流的抗噪耳機當中，主動式噪音控制(Active Noise Control, ANC)通常用於降低低頻域噪音，而高頻噪音則藉由耳罩的材質、機構與密閉性來作被動式的衰減。在現在常見的主動式降噪系統中，大多使用高速數位訊號處理器來進行消除擾人噪音的運算，這為市面上商品化的ANC產品帶來高功耗而造成續航力不足的問題。然而，大部分的ANC耳機所開發的演算法建立在簡單的模擬而忽視實際運作下的限制，這些限制對於ANC的功耗是非常顯著的。本論文提出一個使用於高保真入耳式耳機，基於Adaptive Filtered-x Least Mean Square (FxLMS)演算法架構下的ANC電路之實現，並在擁有多樣性與高擴展性的前提，提出了新的方法來設計VLSI結構。所提出的設計包含了選擇適當的濾波器長度、低功率貯存機制的摺積、平行運算和高傳輸量管路架構，提供了不管在演算法、結構、邏輯和電路上達到高噪音衰減量的表現與低功耗的目標。在這些技術之下，本論文提出兩個設計範例－(1)基於前饋式FxLMS之低功率寬頻帶噪音消除之VLSI電路設計，(2)高效回授式主動噪音消除之VLSI電路設計。設計(1)在需要的高複雜度運算和成本的雙麥克風架構下，使用20MHz的工作時脈、84.2k個gate count之下，僅需要6.59mW的功率消耗，並在寬帶的粉紅噪音測試中，50Hz到1500Hz之間可以達到最大15dB的衰減量。設計(2)在單麥克風的情況下，可以做到最寬到600Hz與15dB的噪音衰減量。本論文使用TSMC 90-nm CMOS製程，所設計的兩個電路工作時脈皆為20MHz，此晶片成功驗證所提出之設計的正確性和實用性，成功達到的高噪音衰減，高傳輸速率與低功率消耗的需求。

Conventional active noise control (ANC) headphones often perform well in reducing the low-frequency noise and isolating the high-frequency noise by earmuffs passively. The existing ANC systems often use high-speed digital processors to cancel out disturbing noise, which result in high power consumption for a commercial ANC headphone. While ANC headphone applications are strongly influenced by practical constraints, most previous works developing algorithms for ANC headphones are based on simplified simulations only and neglect practical limitations. This dissertation proposes a dedicated ANC circuit implementation based on the well-known adaptive filtered-x least mean square (FxLMS) algorithm for high fidelity in-ear headphones, which includes the new techniques to design the VLSI architecture that owns both the versatility and scalability. The proposed design techniques which include the proper filter length selection, low-power storage mechanism for convolution, parallel processing, and high-throughput pipelining architecture provide optimization in the view points of algorithmic, architectural, logic, and circuit levels to achieve high noise reduction performance and low-power design goals. Using those techniques, this dissertation proposes two design examples which are (1) a low-power broad-bandwidth noise cancellation VLSI circuit design based on well-known feed-forward FxLMS algorithm, and (2) a high-performance feedback active noise cancellation VLSI circuit design. The design (1) can attenuate 15 dB for broadband pink noise between 50 and 1500 Hz when operated at 20-MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.59 mW only, with constraints from higher cost and more complex due to it requires two microphones from the hardware structural view point. The design (2) can achieve 15 dB noise reduction and up to 600 Hz attenuation bandwidth, while using only one microphone and is not influenced by the causality constraint. Using the TSMC 90-nm CMOS technology, the optimum operating frequencies of the both proposed designs are 20-MHz which achieve good noise reduction, high data throughput rate, and low-power consumption. The success of this chip implementation proves the correctness and practicability of the proposed design techniques.

Acknowledgement.........................................................................................................I
Abstract........................................................................................................................II
Contents......................................................................................................................VI
Figure Captions.......................................................................................................VIII
Table Captions..........................................................................................................XII
Chapter 1: Introduction ..............................................................................................1
1.1 Evolution of ANC Systems……………………………...........……………….1
1.2 Implementation Challenges of ANC systems....……...…….………………….6
1.3 Research Objectives ......……...……………………………………………….9
1.4 Dissertation Organization.....……...…………....…………………………….11
Chapter 2: A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design ..........................................................................................................................14
2.1 Introduction……………......……...………………………………………….16
2.2 Proposed Adaptive Feed-forward FxLMS ANC Architecture Design …........19
2.2.1 Design Considerations……………............…………………………….19
2.2.2 Proposed Hardware Architecture for the ANC In-Ear Headphone.........27
2.3 Implementation Results……………............……..…………….…………….41
2.4 Performance Evaluation and Comparison ……………..…………………….44
2.5 Summary……………............…………………………………..…………….49
Chapter 3: A High-Performance Feedback FXLMS Active Noise Cancellation VLSI Circuit Design ...................................................................................................51
3.1 Introduction…………..…........………………….……………..…………….53
3.2 Dedicated Adaptive Feedback FxLMS ANC Architecture Design…………..57
3.3 Implementation Results ……………………………………………………...68
3.4 Experiments and Performance Evaluation……………………………….......73
3.5 Summary…………………………………………………………………..….78
Chapter 4: A Chip Implementation .........................................................................80
4.1 Introduction…………..…........………………….….…….........…………….80
4.2 Design Process…………..…........……………………..….........…………….81
4.3 Measuring Results…………..…........…………………….........…………….83
4.4 Summary…………..…........………...……….….…….........………..……….86
Chapter 5: Conclusions and Future Works .............................................................87
5.1 Conclusions…………..…........………………….….…….........…………….87
5.2 Future Works…………..…........……...………….….……………………….88
REFERENCES………………………………………………………………………...89
VITA
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