臺灣博碩士論文加值系統

隨著科技發展快速，金氧半導體元件已發展至奈米等級，電晶體尺寸的持續縮小面臨多種挑戰，例如薄的閘極氧化層會導致載子有直接穿隧的效應、提高了閘極漏電流和較高的臨界電壓(threshold voltage, VT)使得驅動電流有降低的效應。使用HK/MG技術是一個不錯的選擇，可以改善前述的問題。採用HK/MG技術也可以容許些許調整臨界電壓和降低功率消耗、延遲時間。為了避免HK與通道表面之間的界面密度增加，沉積適當的界面層(interfacial layer)是值得關注的技術。然而，加厚界面層會減小整體介電層的介電係數，如此一來，提高驅動電流的主要目的即受打則扣。因此界面層厚度的的控制是非常重要的。另外採用閘極後製程(gate-last)可以避免源/汲極離子佈值後使用退火溫度，而使金屬閘極熔化。利用HfOx/ZrOy/HfOx (HZH)沉積作為閘極介電質，可以提供相對應的介電係數。沉積ZrOy除了作為閘極介電質可以提高K值外，也可以提高HfOx的結晶溫度，並降低閘極漏電流。
以討論28奈米等級元件為本次研究，閘極介電層材料則選擇使用含氧化鉿/氧化鋯/氧化鉿(HfOx/ZrOy/HfOx, HZH)高介電係的數材料，以及使用含氮化去耦合電漿(DPN)製程和沉積後高溫退火製程元件(PDA)，應用在HZH的退火中，探討此等HK/MG pMOSFETs 元件電特性，並比較在不同的氮濃度與退火溫度下之電元件特性。另亦探討HK/MG結合CESL應變技術下，在不同通道長度與量測溫度下的元件電特性。

Following the advanced process technology entering the nano-scale era, the semiconductor industry due to the feature-size shrinkage of semiconductor devices confronts several barrier challenges, such as a thin gate oxide layer causing carrier direct tunneling and a higher threshold voltage (VT) bringing about the possibly lower drive current. Adopting high-K and metal gate (HK/MG) technologies is a suitable choice to alleviate these previous problems. Using HK/MG technology also benefits to freely adjust the threshold voltage and diminish the power consumption or delay time due to the lower gate resistance in the circuit concern. To avoid the over interface state density between HK and channel surface, growing an appropriate interfacial layer (IL) as a buffer layer is noteworthy. However, the thicker IL decreases the chief purpose of depositing HK dielectric to improve the drive current. The thickness control for IL is very essential. Employing gate-last (GL) process is able to avoid the higher source/drain annealing temperature causing molten metal gate and harming process integration. Utilizing sandwiched HfOx/ZrOy/HfOx (HZH) as a gate dielectric appears an adequate method to supply a plentiful relative dielectric constant. Depositing ZrOy as gate dielectric can provides a higher k-value.
In this project, HfOx/ZrOy/HfOx as gate high-K material applied to 28nm devices was adopted. Furthermore, the decoupled plasma nitridation (DPN) process and the post deposition annealing (PDA) were employed during HZH annealing. Probing variables of the annealing temperature and the nitrogen concentration in DPN process influencing the device performance is a beneficial task in yield improvement. When the strain technology was also utilized, the device performance in different channel lengths and measured temperatures will depict the exploratory topics.

摘 要 I
Abstract II
誌謝 III
目 錄 IV
表目錄 VI
圖目錄 VII
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
第二章 半導體元件物理概念 3
2.1 MOSFET 基本結構與特性 3
2.2 能帶(energy band)與能隙(energy gap)結構 5
2.3 載子的傳輸現象 7
2.4 P-N 接面的基本結構與特性 9
2.5 偏壓與內建電位 11
2.6 MOSFET元件輸出特性曲線 13
2.7 MOSFET元件轉移特性曲線 15
2.8 MOSFET元件物理特性 17
2.9 其它重要元件參數與特性 19
2.9.1 次臨界特性 19
2.9.2 臨界電壓的調整 20
2.9.3 遷移率退化 21
2.10 短通道效應 22
2.10.1 臨界電壓的下滑 22
2.10.2 汲極引發的能障下降 23
2.10.3 貫穿效應 24
2.11 降低短通道效應的製程方法 26
2.12 矽晶體的結構 27
第三章 高介電係數材料與製程整合 30
3.1 高介電係數材料/金屬閘極 30
3.1.1 簡介 30
3.2 高介電係數介電層的需求與特性 31
3.2.1 高介電係數材料的選擇 32
3.2.2 介電常數和導電帶能階差大小 34
3.3 薄膜型態 36
3.3.1 熱穩定性問題 37
3.3.2 界面品質 37
3.3.3 閘極相容性 38
3.3.4 製程整合相容性和可靠度問題 40
3.3.5 高介電係數介電層的元件製程 42
第四章 實驗結果 43
4.1 實驗架構說明 43
4.2 量測機台簡介 44
4.3 元件介紹 49
4.4 實驗條件 50
4.5 實驗結果 51
4.5.1 使用高介電係數元件的差異實驗 51
4.5.2 第一階段實驗結果 54
4.5.3 第二階段實驗結果 62
第五章 結論 66
參考文獻 67
作者簡介 70

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