臺灣博碩士論文加值系統

隨著無線通訊系統急速的發展，越來越多無線通訊規格在我們生活中被使用著。因此將多規格無線通訊系統合併為單一的無線收發器是一項重要的研究課題。其中的關鍵技術為一個寬頻段的前端電路設計。本文著重於設計一個寬頻段多規格的射頻功率放大器電路應用於802.11b、802.11g/n所使用之2.45GHz ISM頻帶，UWB-WiMAX 802.16a所使用之3.5G頻帶、IEEE 802.11a 所使用之5GHz U-NII頻帶等規格。我們所提出的寬頻段多規格功率放大器適用於直接降頻收發機架構，使用硬體共用的概念達到減少面積和降低功率消耗的優點。我們所提出的電路使用TSMC CMOS 0.18 微米製程實現，整體面積為0.391平方毫米，功率消耗為805毫瓦，電源電壓為3.3伏特。我們所提出的寬頻段功率放大器可適用於2.45GHz、3.5GHz和5GHz 等頻段，為一個三級的放大器，其中第一跟第二級放大器採用我們所提出的雙迴路迴授技術可達到寬頻及阻抗匹配的特性,達到2~6GHz寬頻及輸入端跟輸出端阻抗匹配50 ohm，使其方便跟第三級的功率放大器輸入端達到極間匹配的效果，第三級放大器具有功率放大的效能。

As the demand of wireless system increases rapidly, more and more wireless communication standards are used simultaneously in our lives. Therefore, a multi-standard communication system that can be integrated into a single wireless transceiver becomes an important research issue. The dominant technique to achieve highly-integrated transmitter architecture is the wideband power amplifier circuit design.
This Thesis is focused on a broadband and multi-standard RF power amplifier for 2.45GHz ISM 802.11b, 802.11g/n, Bluetooth, 3.5G UWB-WiMAX 802.16a, and 5GHz U-NII IEEE 802.11a applications. The proposed broadband and multi-standard RF power amplifier adopts a direct-conversion architecture, thus reducing chip area and power consumption by hardware sharing. The post-simulation results show that the broadband power amplifier occupies an area of 0.391 mm2, dissipating 805mW at high-gain mode with a 3.3V power supply in TSMC CMOS 0.18μm process.
The broadband power amplifier configured in 2.45G, 3.5G, and 5GHz bands is composed of three stages. The first-stage and second-stage amplifiers are based on our proposed dual-loop feedback technique [8][9][10] to reach broadband and impedance matching; they have a wideband input/output 50 ohm matching from 2GHz to 6GHz to achieve inter-stage matching with the third-stage amplifier. The third-stage amplifier is for power amplification.

ABSTRACT i
LIST OF FIGURES vii
LIST OF TABLES xi
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 3
CHAPTER 2 FUNDAMENTAL CONSIDERATION IN RF SYSTEM 5
2.1 Adjacent Channel Power Ratio and Transmitter Spectral Mask 5
2.2 Transmitter Error Vector Magnitude 6
2.3 Linearity 7
2.3.1 One dB Gain Compression Point 7
2.3.2 Third-Order Inter-Modulation 8
2.3.3 Peak-to-Average Power Ratio 10
2.4 Dynamic Range 11
2.5 Specification and Summary 11
CHAPTER 3 TRANSMITTER ARCHITECTURES 13
3.1 Transmitter Architectures 14
3.2 Summary of Transmitter Architectures 15
3.3 Broadband Transmitter Architecture 15
3.4 802.11 Standards 17
3.4.1 802.11b/g Operating Channel 17
3.4.2 802.11a Operating Channel 18
3.4.3 WiMAX 802.16 19

CHAPTER 4 DUAL LOOP FEEDBACK BROADBAND POWER AMPLIFIER .21
4.1 Linear RF Amplifier Theory 21
4.1.1 IV Cure and Loadline 23
4.1.2 Power Added Efficiency 24
4.2 Conduction Angle and Waveform Analysis 24
4.2.1 Comparisons of PA Modes 26
4.3 Multistage PA Design 28
4.4 Class A Power Amplifier Design 29
4.4.1 Load Line Theory for Power Stage Design 29
4.4.2 Load-Pull Contours 31
4.4.3 Gain Match and Power Match 32
4.4.4 Power Amplifier Stage Load Line and Load Pulling Simulation 33
4.5 Negative Feedback Amplifier 35
4.6 Dual Feedback Amplifier 36
4.6.1 Inductive Peaking Techniques 38
4.6.2 Capacitive Peaking Techniques 39
4.6.3 Voltage and Current Gains 40
4.6.4 Input and Output Impedances 41
4.6.4 Closed-Loop Poles 42
4.7 Broadband Amplifier with Darlington Frequency Doubler 43
4.8 Driver Amplifier Simulation Results 44
CHAPTER 5 A 2GHz to 6 GHz Broadband Power Amplifier 47
5.1 Three-Stage Broadband Power Amplifier Design Flow 48
5.2 Pre/Post Simulation Results 50
5.3 Corner Simulations of One dB Comparison Point 54
5.4 Spectrum Mask and EVM Simulation 56
5.5 Measurement Results 57
5.6 Summary.......................................... 61
CHAPTER 6 CONCLUSION................................. .63
REFERENCE .......................................... 65

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