臺灣博碩士論文加值系統

半導體製程技術的持續進步，使得系統單晶片的實現得以成功。系統單晶片
的效能與複雜度維持穩定的成長。然而，晶片中訊號的繞線複雜度與電子雜訊的
大小也隨之增加。據我們所知，當電磁干擾降低系統的穩定度與可靠度時，其也
逐漸變成一個棘手的問題。為了緩和這個問題，屏蔽的方法曾經被採用，但是與
展頻時脈電路相比它的成本卻高出許多。因此，目前展頻時脈電路成為一個熱門
的研究題目。
本論文提出一個全數位可程式化的展頻時脈產生器，其可由使用者設定展頻
模式與展頻的比例。在展頻時脈產生器的設計中，使用了以改良式連續近似暫存
器為基礎的控制器來加快展頻時脈產生器於中心頻率的鎖定時間。再者，同時也
採用了以數位對時間轉換器為基礎的頻率合成器來擴展展頻時脈產生器的操作
頻率範圍。
在TSMC 0.18-μm 1P6M CMOS 製程且操作電壓1.8V 條件下，HSPICE 電路
模擬結果顯示電路可操作輸入訊號頻率範圍為70MHz～150MHz 與輸出訊號頻
率範圍為35MHz～600MHz。展頻模式為設定為向下、中心、向上三種模式與展
頻比例範圍可設定為5%～10%。當展頻時脈產生器的輸出工作頻率在600MHz
且展頻比例為10%，其功率消耗為2.42mW 且電磁干擾可衰減20.3dB。

Continuing advance of the semiconductor process technology enable the
successful realization of the System-on-a-Chip (SoC). The performance and the
complexity of SOCs keep grow steadily. However, the signal routing complexity
inside the chip itself as well as the level of electronic noise will also increase. To the
best of our knowledge, the Electro Magnetic Interference (EMI) will gradually
become an issue, since it will decrease the stability and reliability of a system. In
order to alleviate this problem, shielding method has been adopted, but it has much
higher cost compared to the spread spectrum clock circuit. Thus, the spread spectrum
clock circuit has become more popular object of research than shielding method.
This paper presents an all-digital programmable spread spectrum clock generator
(SSCG) that allows user to program the operation mode as well as the spread ratio. In
the design of proposed SSCG, an improved successive approximation register based
controller is adopted to accelerate the locking time of center frequency of SSCG.
Furthermore, a digital-to-time converter based frequency synthesizer is also applied to
extend the operating frequency range of SSCG.
The proposed SSCG has been designed based on 0.18-μm 1P6M CMOS
technology with a 1.8V power supply voltage. The HSPICE simulation results show
that the acceptable frequency of input clock ranges from 70MHz to 150MHz, and the
frequency of output clock ranges from 35MHz to 600MHz. When the SSCG operated
at 600MHz, the overall power consumption is about 2.42mW and it achieves a 20.3dB
EMI reductions with 10% spreading ratio

摘要............................................................................................................................... I
英文摘要....................................................................................................................... II
圖目錄..........................................................................................................................VI
表目錄..........................................................................................................................IX
專有名詞中、英文對照表...........................................................................................X
第一章 緒論..................................................................................................................1
1-1.研究背景.........................................................................................................1
1-2.研究動機.........................................................................................................1
1-3.電磁干擾簡介.................................................................................................1
1-4.積體電路現有防治電磁干擾的技術.............................................................2
1-5.論文架構.........................................................................................................3
第二章 展頻技術與調變參數分析..............................................................................4
2-1.展頻之基本理論.............................................................................................4
2-2.展頻技術在時間域上的影響.........................................................................8
2-3.調變參數的影響.............................................................................................9
2-4.調變參數對抑制電磁干擾的實驗歸納.......................................................11
2-5.應用展頻技術的考量與限制.......................................................................12
第三章 傳統展頻時脈產生器之電路架構................................................................13
3-1.鎖相迴路的基本原理...................................................................................13
3-2.展頻時脈產生器的分類...............................................................................16
3-3.以鎖相迴路為基礎的展頻時脈產生器.......................................................18
3-4.以延遲線為基礎的展頻時脈產生器...........................................................23
3-5.文獻綜合分析與架構設計趨勢...................................................................25
第四章 新型全數位可程式化展頻時脈產生器的架構與原理................................27
4-1.設計概念.......................................................................................................27
4-1-1.多相位時脈產生器............................................................................28
4-1-2.頻率合成器........................................................................................32
4-2.新型全數位可程式化展頻時脈產生器完整架構.......................................37
第五章 新型全數位可程式化展頻時脈產生器的子電路設計................................44
5-1.多相位時脈控制器.......................................................................................44
5-1-1 時間數位轉換器................................................................................44
5-1-2 改良式連續近似暫存器....................................................................45
5-1-3 相位檢測器........................................................................................46
5-1-4 時序控制單元....................................................................................48
5-2.數位控制延遲線...........................................................................................50
5-2-1 細調延遲單元....................................................................................51
5-2-2 粗調延遲單元....................................................................................53
5-2-3 數位控制振盪器模式........................................................................54
5-3.頻率合成器...................................................................................................57
5-3-1 數位至時間維度轉換器...................................................................57
5-3-2 數位碼字集單元...............................................................................59
5-3-3 時脈產生器.......................................................................................61
5-4.展頻時脈控制器...........................................................................................62
5-4-1 邊界限制電路....................................................................................62
5-4-2 同步上數/下數計數器.......................................................................63
5-4-3 比較單元............................................................................................63
5-4-4 前瞻進位加減法器............................................................................65
5-4-5 路徑選擇器........................................................................................70
第六章 新型展頻時脈產生器的模擬結果................................................................71
6-1.新型全數位可程式化展頻時脈產生器的模擬結果...................................71
6-2.新型全數位可程式化展頻時脈產生器的模擬規格...................................77
6-3.電路功率消耗...............................................................................................78
6-4.效能比較.......................................................................................................79
第七章 結論與未來展望............................................................................................81
參考文獻......................................................................................................................82

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