臺灣博碩士論文加值系統

快閃式類比數位轉換器 (Flash A/D Converter) 是目前最快的一種架構，然而在提高解析度時，整體面積與消耗功率卻呈現大幅度的增加。因此，管線式類比數位轉換器 (Pipelined A/D Converter) 相較於快閃式類比數位轉換器更適合發展快速與高解析度的架構。然而此種架構的效能往往取決於所使用的運算放大器，所以運算放大器的設計常常為管線式類比數位轉換器的設計重點。
有別於一般的設計方式，我們採用了電流傳輸器 (Current Conveyor) 而非運算放大器為整體電路的核心架構設計出新型的管線式類比數位轉換器。使用電流傳輸器所完成的部分為前端的取樣電路和相乘式數位類比轉換器 (MDAC)。 而在子類比數位轉換器中的比較誤差我們採用了數位修正的方式來完成除錯補償以達到更佳的效能。整個晶片電路以台灣積體電路公司(TSMC) 0.35μm 2P4M製程來實現，根據 HSPICE 的模擬結果，其解析度為八位元，取樣頻率為十百萬赫茲，在3.3V的操作電壓下功率消耗為29mW，DNL與INL分別為 0.5LSB與 0.7LSB。晶片有效面積為0.85x0.85mm2，且此晶片已經由國家晶片中心 (CIC) 審核通過即將下線中。

Flash Analog-to-Digital Converter (ADC) is the fastest one among all the other ADC architectures. However, the power consumption and the chip size will become extremely large as the resolution increased. The pipelined architecture is more suitable for some applications with the requirements of high resolution and high speed than those flash architectures, due to its small size and low power consumption. The accuracy of the pipelined ADC architecture based on the operational amplifier (OPA) is always depended on the OPA performance. As the result, designers always focus on the design of the OPA for the pipelined ADC.
Unlike other designs, we use the second-generation current conveyor (CCII) as the core to design the pipelined ADC instead of the traditional operational amplifier. The new current conveyor based on sample-and-hold (S/H) circuit and MDAC circuit is employed for our design, and the digital error correction technique is applied to increase the performance of our pipelined ADC. The pipelined ADC is designed and implemented with TSMC 0.35μm 2P4M CMOS process. With the HSPICE simulation results, the resolution of the ADC is 8-bit, the sampling rate is 10MHz, and the power consumption is 29mW in 3.3V supply voltage. The DNL and INL are 0.5LSB and 0.7LSB, respectively. The core size is 0.85x0.85mm2. The chip have been sent to CIC for manufacturing.

中文摘要 .i
英文摘要 .ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 .vii
第一章 序論. 1
1.1 相關研究發展近況 1
1.2 研究動機 3
1.3 論文架構 3
第二章 類比數位轉換器架構介紹 5
2.1 類比數位轉換器的特性參數 5
2.2 常見的類比數位轉換器架構 8
2.2.1 快閃式類比數位轉換器 8
2.2.2 兩段式類比數位轉換器 9
2.2.3 管線式類比數位轉換器 11
2.2.4 平行處理式類比數位轉換器 12
2.3 錯誤更正與單級1.5位元之原理 13
第三章 以電流傳輸器設計之管線式類比數位轉換器 19
3.1 整體管線式類比數位轉換器架構 19
3.2 電流傳輸器 20
3.3 取樣保持電路 22
3.3.1 CMOS開關 22
3.3.2 一般型取樣保持電路 25
3.3.3 以電流傳輸器建構的取樣保持電路 26
3.4 相乘式數位類比轉換器 27
3.4.1 一般型相乘式數位類比轉換器 28
3.4.2 以電流傳輸器建構的相乘式數位類比轉換器 29
3.5 比較器 30
3.6 延遲電路與數位更正電路 32
3.7 時脈產生器 35
第四章 模擬結果 37
4.1 電流傳輸器的模擬結果 37
4.2 取樣保持電路與相乘式類比數位轉換器的模擬結果 38
4.3 比較器的模擬結果 41
4.4 時脈產生器的模擬結果 43
4.5 管線式類比數位轉換器的模擬結果 43
第五章 佈局與測試考量 48
5.1 佈局考量 48
5.2 測試方法 55
第六章 結論與後續研究 58
6.1 結論 58
6.2 後續研究 58
參考文獻 59
附錄A
The 2004 VLSI Design/CAD Symposium 投稿論文
『New CCII-based Sample-and-Hold and MDAC Circuits for Pipelined ADC』 62

[1] Shang-Yuan Chuang and Terry L. Sculley, “A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter,” IEEE Journal of Solid-State Circuits, vol. 37, no. 6, pp. 683-674, June 2002.
[2] Yuh-Min Lin, Beomsup Kim, and Paul R. Gray, “A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 628-636, April 1991.
[3] Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[4] G. Miller, M. Timko, H.-S. Lee, E. Nestler, M. Mueck and P. Ferguson, “An 18 b 10 self-calibrating ADC,” IEEE International Solid-State Circuits Conference, pp. 168-169, 1990.
[5] Hsin-Shu Chen, Bang-Sup Song, and Kantilal Bacrania, “A 14-b 20-MSamples/s CMOS Pipelined ADC,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 997-1001, June 2001.
[6] D. Miyazaki, S. Kawahito and M. Furuta, “A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture,” IEEE Journal of Solid-State Circuits, vol. 38, Issue 2, pp. 369-373, Feb. 2003.
[7] W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song, “A 10-b 20-Msample/s Low-Power CMOS ADC,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pp. 514-521, May 1995.
[8] Jun Ming and Stephen H. Lweis, “An 8-bit 80-Msamples/s Pipeline Analog to Digital Converter With Background Calibration,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, pp. 1489 -1497, May 2001.
[9] Yuh-Shyan Hwang, Pei-Tzu Hung, Wei Chen, and Shen-Iuan Liu, “Systematic generation of current-mode linear transformation filters based on multiple output CCIIs,” Analog Integrated Circuits and Signal Processing, vol. 32, pp. 123-134, 2002.
[10] Dong-Shiuh Wu, Shen-Iuan Liu, Yuh-Shyan Hwang, and Yan Pei Wu, “Multiphe-phase sinusoidal oscillator using second-generation current conveyors,” International Journal of Electronics, vol. 78, no.4, pp. 645-651, 1995.
[11] B. Wilson, “High-performance current conveyor implementation,” Electronics Letters, vol. 20, pp. 990-991, Nov. 1984.
[12] 謝晉昇, Nyquist-Rate A/D Converter Design, Chip Implementation Center, 2001.
[13] C. Z. Portmann and T. H. Y. Meng, “Power-efficient metastability error reduction in CMOS flash A/D converters,” IEEE Journal of Solid-State Circuits, vol. 31, no. 8, Dec. 1992, pp. 1132-1140.
[14] Behzad Razavi “Principles of Data Conversion System Design,” IEEE Press 1995.
[15] Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2000.
[16] B Razavi and B. A. Wooley, “A 12-b 5Msample/s Two-Step CMOS A/D converter,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1667-1678, 1992.
[17] Bang-Sup Song, Seung-Hoon Lee and Michael Tompsett, “A 10-b 15MHz CMOS Recycling Two-Step A/D Converter,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp1328-1337, 1993.
[18] H. van der Ploeg and R. Remmers, “A 3.3V 10b 25 Msample/s two-step ADC in 0.35um CMOS,” IEEE International of Solid-State Circuits Conference, pp. 318-319, 1999.
[19] L. Sumanen, M. Waltari and K. A. I. Halonen, “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE Journal of Solid-State Circuits, vol. 36 Issue: 7, pp. 1048-1055, July 2001.
[20] T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 308 —317, March 2000.
[21] Stephen H. Lewis and Paul R. Gray, “A Pipelined 5 Msample/s 9-bit Analog to Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 954-961, 1987.
[22] Stephen H. Lewis, R. Ramachandran and W. Martin Snelgrove, “Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy,” IEEE Transactions on Circuits and System II: Analog and Digital Signal Processing, vol. 42, no. 7, pp. 437-445, July 1995.
[23] I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318-325, 2000.
[24] K. C. Smith and A. Sedra, “second-generation current conveyor and its applications,” IEEE Transactions on Circuits and Systems, pp. 132-134, 1970.
[25] F. Sequin and A. Fabre, “New second generation current conveyor with reduced parasitic resistance and bandpass filter application,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48 Issue: 6, pp.781-785, June 2001.
[26] P. A. Martinez, J. Sabadell, C. Aldea and S. Celma, ”Variable frequency sinusoidal oscillators based on CCII+,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46 Issue: 11, pp. 1386-1390, Nov. 1999
[27] H. A. Alzaher, H. Elwan and M. Ismail, “A CMOS fully balanced second-generation current conveyor,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50 Issue: 6, pp. 278-287, June 2003.
[28] Alexander A. Tutyshkin and Alexander S. Korotkov, “Current conveyor based switched-capacitor integrator with reduced parasitic sensitivity,” IEEE International Conference on Circuits and Systems for Communications, pp. 78-81, 2002.