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參考文獻
[1]K. Bazargan, S. Kim, M. Sarrafzadeh(1998)” Nostradamus: a floorplanner of uncertain design” Proceedings of the 1998 International Symposium on Physical Design Conference, Pages 18 – 23. [2]Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu (2000) “B*-Trees: A New Representation for Non-Slicing Floorplans” Proceedings of the 37th Design Automation Conference, Pages 458–463. [3]P. N. Guo, C. K. Cheng, and T. Yoshimura (1999) “An O-tree Representation of Non-Slicing Floorplan, and Its Applications” Proceedings of the 36th ACM/IEEE Design Automation Conference, Pages 268–273. [4]X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu (2000) “Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan” Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, Pages 8–12. [5]P. G. Sassone and S. K. Lim (2003) “A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning” Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, Pages 74-80. [6]J. Li, T. Yan, B. Yang, J. Yu, and C. Li (2004) “A Packing Algorithm for Non-Manhattan Hexagon/Triangle Placement Design by Using An Adaptive O-Tree Representation” Proceeding of 41st Design Automation Conference, Pages 646–651 . [7]J. M. Lin and Y. W. Chang (2001) “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans” Proceeding of 38th Design Automation Conference, Pages 764–769. [8]H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. (1996) “VLSI Module Placement Based on Rectangle-Packing by the Sequence–Pair” Proceedings of IEEE Transaction on Computer Aided Design of Integrated Circuits and System, February 1996 Volume 15 Issue 2, Pages 1518–1524. [9]S. Nakata, K. Fujuoshi, H. Murata, and Y. Kajitani (1996)“Module Placement on BSG-Structure and IC Layout Applications” Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, Pages 484–491. [10]H. Onodera, Y. Taniguchi, and K. Tamaru (1991) “Branch-and-Bound Placement for Building Block Layout” Proceedings of 28rd ACM/IEEE Design Automation Conference, Pages 433–439. [11]R. H. J .M. Otten (1982) “Automatic Floorplan Design” Proceedings of 19th ACM/IEEE Design Automation Conference, Pages 261–267. [12]K. Sakanushi, Y. Kajitani, and D. P. Mehta (2003) “The Quarter-State-Sequence Floorplan Representation” Proceedings of IEEE Transaction on Circuits and Systems–I: Fundamental Theory and Applications, March 2003 Volume 50 Issue 3, Pages 376–386. [13]X. Tang, R. Tian, and D. F. Wong (2001) “Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation” Proceedings of IEEE Transaction on Computer Aided Design of Integrated Circuits and System, December 2001 Volume 20 Issue 12, Pages 1406–1413. [14]X. Tang and D. F. Wong (2002) “Floorplanning with Alignment and Performance Constraints” Proceedings of 39th Design Automation Conference, Pages 848–853. [15]D. F. Wong and C. L. Liu (1986) “A New Algorithm for Floorplan Designs” Proceedings of 23rd ACM/IEEE Design Automation Conference, Pages 101–107. [16]H. Xiang, X. Tang, and D. F. Wong (2003) “Bus-Driven Floorplanning” Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, Pages 66 –73. [17]J. Xu, P. N. Guo, and C. K. Cheng (1998) “Rectilinear Block Placement Using Sequence-Pair” Proceedings of the 1998 International Symposium on Physical Design Conference, Pages 173–178. [18]吳彬玄、程仲勝 (2002) “降低電磁干擾之後置平面規劃器”Proceedings of 2002 Taiwan ElectroMagnetic Compatibility Conference, Pages 172–175. [19]吳彬玄、習存榮、程仲勝 (2003)“考慮電磁相容之超大型積體電路平面規劃之研究” Proceedings of 2003 Taiwan ElectroMagnetic Compatibility Conference, Pages 78–83.
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