臺灣博碩士論文加值系統

在本篇論文中，對於各種運用於低電壓放大器的技巧加以分類整理，並說明其電路架構與原理，並針對放大器在低電壓操作時，共模輸入範圍不足的問題，提出雙重P型差動輸入對，雙重P型差動對與基底電流控制法，雙重N型差動輸入對，三種構想設計的放大器，來滿足低電壓下，放大器的共模輸入範圍達到全擺幅的需求。其中、第一種放大器使用雙重P型差動輸入對的架構，結合了一對P型差動輸入對與一對電壓位移P型差動輸入對的架構，在供應電壓一伏特操作時，共模輸入範圍為0.15~0.93V，第二種放大器使用雙重P型差動對與基底電流控制法的架構，利用基底電流控制法，讓差動輸入對的臨界電壓Vt降低，更適合於低電壓下操作，在供應電壓一伏特操作時，其共模輸入範圍為0.02~0.98V，第三種放大器使用雙重N型差動輸入對的架構，結合了一對N型差動輸入對與一對電壓位移N型差動輸入對的架構，在供應電壓一伏特操作時，共模輸入範圍為0.01V~0.97V，這三個放大器是使用TSMC0.35um製程所實現，三個放大器所佔的晶片面積為1476X927um2。本論文成功的實現了三種低電壓放大器，並達成共模輸入範圍全擺幅的需求。

In this work, we present three low-voltage CMOS amplifiers. The first amplifier with dual P-channel differential pairs, that combines a P-channel differential input pair and a level-shift P-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.15~0.93V. The second amplifier with dual P-channel differential pairs and current driven bulk （C.D.B.）skill, that apply C.D.B. skill to reduce Vt of differential pairs , obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.02~0.98V. The third amplifier with dual N-channel differential pairs, that combines a N-channel differential input pair and a level-shift N-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.01~0.97V. These 3 amplifiers are fabricated by TSMC 0.35um. The total chip size is 1476X927um2.

目錄
頁次
中文摘要 …………………………………….…………….……...…… i
英文摘要 ……………………………………….……………….…….. ii
誌謝 …………………………………………………………...….….. iii
目錄 ……………………………………….………………..………... iv
表目錄………………………………………………………….……... vii
圖目錄…………………………………………………………...….…….xi
第一章 導論……………………………..………………….…………….1
1.1研究動機與目的……………………………………….……………....1
1.2 設計考量……………………………………………….…..…1
1.3 論文組織………………………………….……..…………………….3
第二章 低電壓全擺幅放大器先前技術探討……………………………..4
2.1 簡介………………………………………………….……….……….4
2.2 使用多級串接組態之技巧…….……………...…………..…...….4
2.3新式局部電荷幫浦之技巧……………….…………………………..5
2.4基底輸入之技巧………………………...………..…..……….……9
2.5基底電流控制法……………………………………………..…….…10
2.6多重輸入閘極浮接電晶體………………………………………………13
2.7閘極半浮接電晶體………………………………………...…….…..15
2.8前匱式動態電位平移法…………………………………………………17
2.9回授式輸入共模電壓控制法……………………………………………20
2.10前匱式穩定電導輸入端電壓平移法………………………………….23
2.11虛擬電晶體……………………..………………………….....…..25
2.12各種技術分析與整理………………….…………………………...27
第三章 雙重差動輸入對之設計與應用……………………………..……29
3.1前言...…………………………..….…..……………………………29
3.2 P型雙重差動輸入對……………..…………………………….….29
3.2.1原理與電路架構……………………....…………………………..29
3.2.2 動作驗證與模擬………….…………………..…….……...….34
3.2.3晶片佈局……………….….…………………..…….………..….36
3.2.4晶片佈局後驗證模擬與角落模擬………..…..…….………..….41
3.3 P型雙重差動輸入對與基底電流控制法……………..……….……43
3.3.1原理與電路架構……………………....…………………………..43
3.3.2 動作驗證與模擬………….…………………..…….………..….45
3.3.3晶片佈局……………….….…………………..…….………..….47
3.3.4晶片佈局後驗證模擬與角落模擬………..…..…….………..….49
3.4 N型雙重差動輸入對…………………...……………..……….……50
3.4.1原理與電路架構……………………....…………………………..50
3.4.2 動作驗證與模擬………….…………………..…….………..….51
3.4.3晶片佈局……………….….…………………..…….………..….54
3.4.4晶片佈局後驗證模擬與角落模擬………..…..…….………..….60
第四章 晶片測量……………………..…………………………..…....62
4.1 放大器量測方式………………………………………………..……62
4.2 P型雙重差動輸入對放大器之量測結果………….….………….…65
4.3 P型雙重差動輸入對+基底電流控制法放大器之量測結果…………..72
4.4 N型雙重差動輸入對放大器之量測結果……………………………….79
4.5三種放大器的比較與分析………………………………………………85
4.6 討論……………………………..……………………………………87
第五章 總結與未來研究方向…………………………………….……...90
5.1總結……………………………….…………………….……..…….90
5.2未來研究方向……………………….……………………....……..90
參考文獻……………………………………………………………………....….92
簡歷………………………………………………………………………… 95
附錄 (會議投稿論文)…………………………………………..…………96

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