臺灣博碩士論文加值系統

　　隨著微縮化MOSFET元件汲極與源極間寬度的特徵尺度（feature size）已進入深次微米的世代，降低閘極絕緣層（SiO2或SiONx）的厚度增加單位面積閘極的電容值，以提高閘極對通道區內少數載子的控制能力已成為一必然趨勢。然受限於閘極漏電流係隨著二氧化矽閘極絕緣層厚度之減少以指數方式增加，乃使以二氧化矽為閘極絕緣層之最低厚度將達到某一物理極限值。使用高介電係數（high-k）絕緣材料作為MIS穿透結構閘極絕緣層，於獲得相同閘極電容值條件下，可允許採用較二氧化矽厚度 k/3.9 倍之厚度以抑制閘極漏電流，已成為新世代CMOS製程之發展趨勢之ㄧ。

　　高介電係數閘極絕緣層材料之使用，雖可延續CMOS製程技術持續微縮之動力，然除了高介電係數材料與矽半導體之介面品質及與閘極材料製成相容性問題仍待深入驗證或克服外，任何高介電係數材料於CMOS製程技術持續微縮過程中，仍將面臨與今日二氧化矽之相同課題，亦即閘極漏電電流或厚度最低極限問題。於考慮高介電係數閘極材料/矽通道界面品質與其間載子各種可能傳導，進而估算可應用於新世代CMOS製程技術高介電係數閘極材料之最低厚度或最小氧化層等效厚度(minimum equivalent oxide thickness, EOT(min))，乃成為高介電係數閘極材料ㄧ極重要之可行性評估依據。

　　本論文提出一理論模型，針對MIS穿透結構進行模擬分析。於介電材料/矽半導體接面間，考慮介面態位(interface state)電荷非線性的分布及其可能之載子傳導，推導電位分布及閘極電流傳導之相關方程式並進行自洽(self-consistent)計算，模擬分析MIS穿透結構操作在堆積(accumulation)、空乏(depletion)及強反轉（strong inversion）條件下閘極電流與電壓的曲線圖（I－V curve），並與實驗資料作比較討論；再依據此理論架構，提出一由外部提供額外少數載子源(external inject current)的觀念，藉此來平衡載子蕭基放射電流、介面態位對閘極漏電流、少數載子（電子）的閘極穿遂電流、少數載子（電子）在空乏區內的再結合電流及少數載子（電子）於電場的作用下對閘極的Fowler－Nordheim tunneling電流的影響，使MIS穿透結構可操作在強反轉模式且達到穩定平衡（steady－state condition）時，必須滿足少數載子的電流連續（current continuity）方程式。進而求得在不需要外加少數載子電流源的條件下 ，MIS穿透結構可操作在強反轉模式時的絕緣層最小厚度EOT(min) 與介面態位電荷密度、不同介電值絕緣層、半導體內部摻雜濃度與閘極金屬功函數材料關係。

　　依據本論文的理論模型，吾人以P型矽半導體為基板（NA=4E16cm-3），金屬Pt為閘極（功函數為5.3eV），考慮單一厚度的陡接面二氧化鉿HfO2為絕緣層（k＝21），其介面態位電荷密度（NIS）為2E12cm-2的MIS元件結構，當元件外加電壓且能夠操作在聚積模式及強反轉模式下，所擷取的穿過二氧化鉿（HfO2）介電層的閘極漏電流，其模擬計算結果各約1E-6到1E-7及1E-7到1E-8 A/cm2，所擷取二氧化鉿（HfO2）絕緣層相對於二氧化矽（SiO2）的厚度為EOT＝1.26nm ∼ 1.48nm，與實驗結果EOT＝1.43nm相符，此結果亦顯示本論文所建立閘極漏電流之模型應屬正確可行。

　　於本論文中吾人所考慮閘極總電流可分為三部份，亦即少數載子（電子）的閘極穿遂電流、介面態位對閘極的漏電流及少數載子（電子）於電場的作用下，對閘極的Fowler－Nordheim tunneling電流 。當討論以金屬為閘極（功函數為4.36 eV），高介電係數薄膜材料（k=25）作為閘極絕緣層的MIS元件，其介面態位電荷密度（NIS）為2E12cm-2，當不需要外加少數載子電流源而可操作於強反轉的模式下，此時EOT(min)約為1.28 nm，此時閘極總電流約為10-7~10-8　A/cm2 。根據本理論計算各個閘極電流分量的結果發現，其中介面態位對閘極的漏電流是最主要的閘極漏電流的貢獻者，此亦與實驗結果相符。

　　隨著MOSFET元件汲極與源極間寬度特徵尺度的微縮化，降低閘極絕緣層的厚度增加單位面積閘極的電容值，以提高汲極端電流的趨動能力是吾人努力的方向。由本論文中指出了有四種方向可供考慮：
(1)　提高閘極絕緣層材料的介電係數值。
(2)　降低介面態位電荷密度。
(3)　降低矽半導體內部雜質摻雜濃度。
(4)　對NMOS而言，降低金屬功函數，即提高閘極金屬功函數與矽半導體費米能階的差值；對PMOS而言則相反。

　　檢視ITRS2006對High-performance logic Technology所公佈的標準，當時間推移至2010年時，其EOT(min)=1.1 nm @ inversion mode。吾人可提出兩種解決方案來滿足此一要求，其一是提高閘極絕緣層材料的介電係數值，此時 k∼40 ＠NIS∼2E12 cm-2。其二是降低介面態位電荷密度的量，此時NIS∼1E10 cm－2 ＠ k∼25。

　　For continuous scaling down of advanced ULSI CMOS technology into deep sub-100-nm regime, further reduction in gate oxide (SiO2 and SiONx) thickness is required. Performance gains obtained from thinning oxide thickness as low as 1 nm no longer exists because gate tunneling leakage becomes a substantial power drain. Under the circumstance, other alternative gate dielectrics with high-dielectric constants (k) must be considered, which allow the use of a physically thicker film while acting electrically as a thin dielectric. Nevertheless, as scaling down of CMOS technology keep continuing in the future, qualified high-k dielectrics should face the same leakage and reliability problem as encountered by thermal oxide. Consequently, it is very important and interesting to clarify the scaling limit of high-k dielectrics for future MOSFETs.

　　In this work, a theoretical model for the simulation of gate current-voltage (I-V) characteristic of tunneling MIS structure is proposed when the MIS tunneling structure operate under accumulation, depletion and strong inversion condition, which we consider carrier transports with the metal gate and the semiconductor via interface states at the I/S interface. For an M/HfO2/p-Si structure with metal work function, k-value, and doping concentration of 5.3 eV, 21, and 4E16cm-3, respectively and both donor- and acceptor-like ISs were assumed having a peak density of 2E12cm-2. the calculated high-k equivalent oxide thicknesses (EOT) is around 1.26nm ~ 1.48 nm. Good agreement with experimental data (EOT=1.43 nm) reported in the literature[1] was obtained.

　　Under an external bias voltage on MIS tunneling structure, once the physical thickness of high-k dielectric is too thin, surface electrons induced by gate voltage will leak to gate metal, therefore, an external injection current is required to sustain the onset strong inversion of the semiconductor. The lower limit of high-k dielectric thickness to sustain onset of strong inversion at the semiconductor surface under a certain bias without external injection currentis then used for EOT(min) calculation. According the proposed inversion criterion and considering direct tunneling of carriers in conduction and valence bands as well as ISs through the high-k dielectric to the metal gate, the dependence of EOT(min) on the k-value of the dielectric, density of ISs NIS, substrate doping concentration NA, and metal work function was presented. It is seen that EOT(min) decreases with increasing the k-value. However, the increase in NIS,NA or metal work function would enlarge the value of EOT(min).

　　In order to meet ITRS2006 High-performance logic technology requirement, EOT(min)=1.1 nm@inversion mode, two solutions have been proposed in this thesis, the first one is to raise the gate dielectric permittivity value to 40 when the interface state density is almost 2E12cm-2; and the other one is to reduce interface state density to 1E10 for a gate dielectric material with a permittivity value of 25.

中文摘要 ii
英文摘要 vi
致謝 viii
目錄 ix
表目錄 xi
圖目錄 xii
第一章 緒論
1.1　MOS元件微縮化所面臨之問題 1
1.2 　研究動機 8

第二章 理論架構
2.1 　非熱平衡狀態下MIS穿透結構之簡易能帶圖 11
2.2　 MIS穿透結構操作在強反轉模式之電位分佈及少數載子電流連續方程式 15
2.3 　閘極介電材料之最小氧化層等效厚度EOT(min) 21

第三章 結果與討論
3.1 　 MIS穿透結構閘極電流-電壓特性模擬結果分析及其與實驗作比較討論 33
3.2 　MIS穿透結構操作於聚積模式及強反轉模式下之EOT(min)計算結果分析討論 36
3.3 　MIS穿透結構介電材料之EOT(min)與閘極漏電流各分量之關係 38
3.4 　MIS穿透結構閘極絕緣層材料電介值與絕緣層最小厚度EOT(min)之關係 41
3.5 　MIS穿透結構閘極介電材料EOT(min)與介面態位電荷密度之關係 45
3.6 　MIS穿透結構閘極介電材料EOT(min)與半導體摻雜濃度之關係度 47
3.7 　MIS穿透結構閘極介電材料EOT(min)與閘極金屬功函數之關係 48

第四章結論與未來研究方向的建議
4.1 　結論 49
4.2 　未來研究方向的建議 53

參考文獻 55
附錄 58
自述 71

[1]　Julie Diane Casperson,“Design and Characterization of Layered Tunnel Barriers for Nonvolatile Memory Applications”, Thesis is for the Degree of Doctor of Philosophy, California Institute of Technology 2004.
[2]　Yee-Chia Yeo; Tsu-Jae King; Chenming Hu, "MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations", Electron Devices, IEEE Transactions on Volume 50, Issue 4, April 2003 Page(s): 1027 – 1035.
[3]　M. L.Green et al., J. Appl. Phys. Vol. 90 No. 5 2001.
[4]　Xin Guo and T. P. Ma, IEEE Electron Device Lett.,Vol. 19 No.6, 1998.
[5]　P. A. Kraus et al., Applied Materials ET Conference, 2003.
[6]　Govoreanu, B.; Blomme, "An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions", Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on Volume , Issue 3-5, Sept. 2003 Page(s): 287 – 290.
[7]　Kang-ill Seo IEEE Annual International Reliability Physics Symposium, p208 (2005).
[8]　Bogdan Govoreanu et al., SISPAD p287 - 290 2003.
[9]　A. Morioka et al., VLSI Tech., p. 65(2003).
[10]　Sanghun Jeon et al., pp. 955, IEDM, 2002.
[11]　Wen-Chin Lee et al., " Modeling CMOS tunneling currents through ultrathin gate oxide dueto conduction- and valence-band electron and hole tunneling"IEEE TRANSACTIONS ON ELECTRON DEVICE, vol.48, No.7, (2001).
[12]　Vogel, E.M.; Ahmed, K.Z.; "Modeled tunnel currents for high dielectric constant dielectrics", Electron Devices, IEEE Transactions on Volume 45, Issue 6, Jun 1998 Page(s):1350-1355.
[13]　S. J. Wang et al., "On occupation functions of donor- and acceptance-like interface states in metal-insulator-semiconductor tunnel structure", Solid-State Electrons Vol. 28. No.12 pp. 1181-1191, 1985.
[14]　S. J. Wang, et al., "On the minority-carrier quasi-fermi level in metal-oxide-semiconductor tunnel structure", Solid-State Electrons, Vol. 29. No.3 pp. 339-353, 1986.
[15]　S. J. Wang et al., "inversion criteria for the metal-insulator-semiconductor tunneling structure". J, Appl. Phys. 60(3), 1 August 1986.
[16]　Madan, A.; Bose, S.C.; George, P.J.; Chandra Shekhar, "Evaluation of device parameters of HfO2/SiO2/Si gate dielectric stack for MOSFETs", VLSI Design, 2005, 18th International Conference on Volume, Issue, 3-7, Jan. 2005 Page(s): 386 – 391.
[17]　Yuan Taun ,Tak H Ning, “Fundamentals of Modern VLSI Device”, 2000.
[18]　Dale L. Critchlow,“MOSFET Scaling- The Driver of VLSI Technology”PROCEEDING OF THE IEEE, Vol. 87, No.4 April 1999.
[19]　International Technology Roadmap for Semiconductor (ITRS), 2005 update.
[20]　Hiroshi Iwai,"CMOS downsizing toward sub-10 nm", Solid-State Electronics 48 (2004) 497–503.
[21]　D. Bauza,"Electrical properties of Si–SiO2 interface traps and evolution with oxide thickness in MOSFET s with oxides from 2.3 to 1.2 nm thick",Solid-State Electronics 47 (2003) 1677–1683.
[22]　Wen-Chin Lee and Chenming Hu, "Modeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling", 2000 Symposium on VLSI Technology Digest of Technical Paper.
[23]　BRUNO RICCO, "Oxide-Thickness Determination in Thin-Insulator MOS Structures", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35. NO. 4, APRIL 1999.
[24]　Thomas Kauerauf, "Scaling CMOS: Finding the gate stack with the lowest leakage current", Solid-State Electronics 49 (2005) 695–701.
[25]　L. Xie, Y. Zhao, M.H. White, "Interfacial oxide determination and chemical/electrical structures of HfO2/SiOx/Si gate dielectrics", Solid-State Electronics 48 (2004) 2071-2077.
[26]　C. Ren, H. Y. Yu, "Fermi-Level Pinning Induced Thermal Instability in the Effective Work Function of TaN in TaN/SiO2 Gate Stack", IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 3, MARCH 2004
[27]　Takeshi Yamaguchi, Hideki Satake, and Noburu Fukushima,"Band Diagram and Carrier Conduction Mechanisms in ZrO2 MIS Structures", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 5, MAY 2004.
[28]　Daniel Bauza,"Extraction of Si-SiO2 Interface Trap Densities in MOS Structures With Ultrathin Oxides",IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 11, NOVEMBER 2002.
[29]　Hongyu Yu,Yong-Tian Hou,“Investigation of Hole-Tunneling Current Through Ultrathin Oxynitride/Oxide Stack Gate Dielectrics in p-MOSFETs", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 7, JULY 2002.
[30]　Sanghun Jeon,Frederick J. Walker, "Epitaxial SrTiO3 on Silicon with EOT of 5.4A for MOS Gate Dielectric Application", IEEE IEDM 2002 Page 955.
[31]　W. K. Henson, K. Z. Ahmed,"Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance–Voltage Measurements on MOS Capacitors", IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 4, APRIL 1999.
[32]　Bai, P.; Auth, C.; Balakrishnan, S.; Bost, M.; Brain, R.; Chikarmane, "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell"Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International Volume , Issue , 13-15 Dec. 2004 Page(s): 657- 660.