臺灣博碩士論文加值系統

隨著積體電路的發展，電晶體單位尺寸一直在微縮，為了保持電晶體良好的電性行為，微縮工程面臨了許多挑戰，如閘極控制能力降低、次臨界擺幅的上升。而高介電常數材料代替傳統閘極氧化層的方式，能有效提升電晶體性能。
本篇論文以高介電常數材料二氧化鉿做為P型多晶矽薄膜電晶體的介電層，並探討氧電漿處理表面的電性行為和可靠度分析。
首先討論常溫下的電性行為，P型多晶矽薄膜電晶體通道表面的懸浮鍵會被氧電漿鈍化，使電晶體有較低的次臨界擺幅。氧電漿處理會在通道表面形成電漿界面層，而電漿界面層含有負的固定氧化層電荷，會有較低的臨界電壓。經過氧電漿處理的P型多晶矽薄膜電晶體，通道表面的應力鍵會增加，導致轉移電導的下降。探討在不同通道長度下，P型薄膜電晶體的次臨界擺幅、臨界電壓、載子遷移率及導通電流。
為了研究可靠度的影響，實驗分為負偏壓應力、負偏壓溫度不穩定性及溫度效應。負偏壓應力狀況下，傳統P型多晶矽薄膜電晶體的次臨界擺幅有嚴重的劣化，是由於在通道表面產生懸浮鍵，且臨界電壓受到次臨界擺幅的影響而劣化。氧電漿處理的通道獲得改善，通道表面產生較少的懸浮鍵和應力鍵，有電洞注入發生，閘極氧化層產生正的固定氧化層電荷，造成臨界電壓的劣化。負偏壓溫度不穩定性，當提高溫度後會造成更嚴重的劣化程度。最後探討溫度效應，比較三種溫度對薄膜電晶體劣化的影響。

With the development of integrated circuits, the transistors dimension has been scaling. In order to maintain the electrical behavior of transistors, miniature engineering faced many challenges. For example, reduced of gate control ability and increased of subthreshold swing. There are many ways to keep the transistors performance. One of the option is using high dielectric constant material instead of the traditional gate oxide layer.
In the thesis, LTPS-TFTs are fabricated with Hafnia oxide gate dielectric and the impact of oxygen plasma induced interfacial layer on electrical behavior of P-type Poly-Si thin film transistors were investigated. First discuss the electrical behavior at room temperature. The transistors with oxygen plasma have less dangling bonds and more strain bonds, leading to smaller subthreshold swing and lower transconductance. The oxygen plasma will grow plasma-induced interfacial layer, it contains negative fix oxide charges, resulting in smaller threshold voltage.
To study the effect of reliability, it was divided into negative bias stress, negative bias temperature instability and temperature effects. In the experiment, the traditional transistors have serious degradation in subthreshold swing. Since the dangling bonds generated on the surface of channel. The transistors with oxygen plasma occurred hole injection in HfO2, producing positive fix oxide charges.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究背景 1
1.2 薄膜電晶體運作原理 2
1.3 晶粒邊界(Grain Boundary)的介紹 2
1.4 短通道效應(Short Channel Effect，SCE) 3
1.5 高介電常數材料 3
1.6 陷阱能態的鈍化 4
1.7 研究動機 5
第二章 實驗參數與元件製作 10
2.1 實驗參數的萃取 10
2.1.1 臨界電壓 10
2.1.2 次臨界擺幅 10
2.1.3 轉移電導 11
2.1.4 電流開啟狀態 11
2.1.5 界面能態密度 11
2.1.6 晶粒邊界陷阱密度 11
2.2 元件的製作 11
第三章 結果與討論 19
3.1 氧電漿處理對P型薄膜電晶體之電性分析 19
3.2 氧電漿處理對P型薄膜電晶體之可靠度分析 20
3.2.1 氧電漿處理對P型薄膜電晶體之NBS分析 20
3.2.2 氧電漿處理對P型薄膜電晶體之NBTI分析 21
3.3.3氧電漿處理對P型薄膜電晶體之溫度效應 22
第四章 結論 38
參考文獻 39

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