臺灣博碩士論文加值系統

本論文提出能提供ZigBee系統運作時所需之頻率合成器，此頻率合成器包含四相位壓控振盪器，並完成設計、模擬與實作。
鑒於ZigBee系統之低功率消耗訴求，本論文考量現行各低功耗之四相位頻率合成器架構後，採取將兩壓控振盪器疊接，即電流再利用(Current Reuse)方式，再加上頂端串接(Top Series)架構之構思，而構成本論文提出之新型四相位壓控振盪器，在低功率消耗下，此電路仍有良好之相位雜訊表現，本四相位壓控振盪器運作於1.8 V電壓之下，只消耗2.61 mW之功率，在自由頻率(Free Running Frequency)時，相位雜訊為-122.5 dBc/Hz。
頻率合成器則進一步將此四相位壓控振盪器整合於其中，以期在通訊系統上能更方便的控制該四相位壓控振盪器，使其輸出系統需要的頻域訊號，設計上從頻率合成器之雜訊研究出發，進而提出合適之設計想法與規格，並在子電路考量上斟酌損益，以期電路運昨時，能達到預期之效果。此頻率合成器之頻率操作區間為 2403 MHz至2478 MHz，鎖定時間為 33μs。頻率合成器之迴路濾波器外接，而頻率合成器運作時，四相位壓控振盪器之功率消耗為2.75 mW，數位部份之電路功率消耗為 12.6 mW，共消耗15.35 mW。運作時所需電壓為1.8 V。

This thesis presents a frequency synthesizer with quadrature VCO for ZigBee system.
To achieve high performance, this thesis proposes a architecture of the quadrature VCO with low-power consumption and low-phase noise. The quadrature VCO in this thesis adopts the stack-up structure to reuse the current, so that the current would flow from PMOS VCO to NMOS VCO, which is called “current reuse”. And a series coupling architecture, which is series connection with the cross coupling pair, is adopted to provide the quadrature signal. Thus a new quardature VCO called “A series coupled current reused quardature VCO” is proposed. The quardature VCO consum 2.61 mW while the supply voltage is 1.8 V. The phase noise is -122.5 dBc/Hz under the free running frequency.
Moreover, the synthesizer contains the quadrature VCO as mention before. It is designed under fully consideration on noise suppression and power consumption. The synthesizer is operated at the frequency between 2403 MHz and 2478 MHz and the settling time is 33 μs. The synthesizer consums 15.35 mW at the supply voltage of 1.8 V.

第一章 緒論............................................................................................................ 1
1-1 壓控振盪器簡介 ........................................................................................... 1
1-2 頻率合成器簡介 ........................................................................................... 5
1-3 ZigBee 系統簡介 .......................................................................................... 7
第二章 分數型頻率合成器介紹與考量 ............................................................... 8
2-1 分數型頻率合成器之運作原理、子電路及轉移函數 ............................... 8
2-1-1 分數型頻率合成器之子電路 .................................................................. 9
2-1-2 分數型頻率合成器之轉移函數 ............................................................ 12
2-2 分數型頻率合成器之雜訊分析 ................................................................. 15
2-2-1 雜訊與充電汞之最大電流 .................................................................... 17
2-2-2 雜訊、壓控振盪器增益、迴路頻寬與除頻器之除率 ........................ 18
2-3 分數型頻率合成器之設計考量 ................................................................. 20
2-3-1 相位雜訊 ................................................................................................. 20
2-3-2 突波 ......................................................................................................... 23
2-3-3 鎖定時間 ................................................................................................ 25
第三章 四相位壓控振盪器之研製 ..................................................................... 27
3-1 四相位壓控振盪器介紹與比較 ................................................................. 29
3-1-1 Superharmonic Coupling ..................................................................... 31
3-1-2 串接式耦合 ............................................................................................ 32
3-1-3 迴路電流再利用 .................................................................................... 34
3-2 串接式耦合迴路電流再利用之四相位壓控振盪器研製 ......................... 37
3-2-1 架構研究 ................................................................................................ 37
3-2-2 相位雜訊之模型與推導 ........................................................................ 38
3-2-3 串接式耦合迴路電流再利用之四相位壓控振盪器之特性考量 ........ 40
3-3 設計、模擬與量測之結果與比較 ............................................................. 45
第四章 應用於ZigBee 系統之頻率合成器設計 ............................................... 53
4-1 ZigBee 系統規範對頻率合成器的影響 .................................................... 53
4-2 由雜訊及迴路頻寬思考頻率合成器 ......................................................... 55
4-3 頻率合成器之整體考量之於子電路設計 ................................................. 57
4-3-1 輸出頻域訊號潔淨度的改善 ................................................................ 58
4-3-2 消耗功率之節約與控制 ........................................................................ 60
4-3-3 鎖定時間的考量 .................................................................................... 63
4-3-4 其他子電路之構思 ................................................................................ 63
4-4 模擬與量測結果與比較 ............................................................................. 66
第五章 結論.......................................................................................................... 77
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5-1 總結.............................................................................................................. 77
5-2 未來工作 ..................................................................................................... 77
參考文獻 ……………………………………………………………………..78

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