臺灣博碩士論文加值系統

　　本文提出具功因校正之單級式電子安定器，其電路架構是由一升壓式功因修正網路與一直/交流轉換器所組成，主要使功因校正電感達到連續電流模式。因為傳統單級式電子安定器係操作於不連續電流模式，因而會有較高之電磁雜訊干擾、較大之電流應力及較大之切換與導通損失的缺點。所以本文提出一升壓式功因修正網路，使功因校正電感達到連續電流模式，來解決傳統單級式電子安定器的缺點。最後本文並實作與設計一額定功率為36W的具功因校正之單級式電子安器，來驗證此單級式電子安定器具有下述之優點：符合IEC 61000-3-2 Class C 國際電氣標準規範、具較小之傳導性電磁雜訊干擾、具較低之電流應力於開關及二極體上。

　　This thesis presents a continuous-current-mode (CCM) single-stage power factor correction (PFC) electronic ballast, which is a combination of a boost-type PFC network and a DC/AC inverter to allow CCM operation for the PFC inductor in the boost-type PFC network. Among the PFC techniques proposed in recent years, in general, the discontinuous-current-mode (DCM) single-stage PFC electronic ballasts have such drawbacks as high electromagnetic interference (EMI), high current stress, and high switching and conduction losses.
　　The PFC capacitor of the developed boost-type PFC network can help the PFC inductor to achieve CCM, thus shaping the input current of the proposed electronic ballast to achieve high power factor (PF).
　　Finally, a 36W rated power electronic ballast prototype circuit is designed and implemented. Experimental results verify the advantages of the proposed ballast; these include the following: the input current harmonics meet the IEC 61000-3-2 Class C Standard, and the ballast offers lower conducted EMI and lower current stress on switches and diodes.

TABLE OF CONTENTS

CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND OF ELECTRONIC BALLAST 1
1.2 POWER FACTOR CORRECTION TECHNIQUES 4
1.3 SINGLE-STAGE PFC OF ELECTRONIC BALLAST 6
1.4 SUMMARY 8
CHAPTER 2 ANALYSIS OF SINGLE-STAGE ELECTRONIC BALLAST 9
2.1 INTRODUCTION 9
2.2 DCM SINGLE-STAGE ELECTRONIC BALLAST 10
2.3 CCM SINGLE-STAGE ELECTRONIC BALLAST 13
2.4 SUMMARY 16
CHAPTER 3 PROPOSED CCM SINGLE-STAGE PFC ELECTRONIC BALLAST 17
3.1 INTRODUCTION 17
3.2 OPERATIONAL PRINCIPLE OF PROPOSED CCM SINGLE-STAGE PFC ELECTRONIC BALLAST 18
3.2.1 Input AC Voltage at Positive Half-cycle 20
3.2.2 Input AC Voltage at Negative Half-cycle 32
3.3 ANALYSIS AND DESIGN CRITERIA 40
3.3.1 Resonant Tank for Optimal Efficiency 40
3.3.2 ZVS Condition 44
3.3.3 Condition of Power Factor Correction 47
3.4 SUMMARY 49
CHAPTER 4 IMPLEMENTATION AND EXPERIMENTAL RESULTS 50
4.1 INTRODUCTION 50
4.2 DESIGN AND IMPLEMENTATION OF A PROTOTYPE CIRCUIT 51
4.3 EXPERIMENTAL RESULTS 58
4.4 SUMMARY 63
CHAPTER 5 CONCLUSIONS AND FUTURE WORK 64
REFERENCES 65

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