臺灣博碩士論文加值系統

隨著時代的進步，科技不斷的演進，電子元件朝向更輕薄短小的方向發展。以致於半導體製程技術已縮小至奈米等級，使得目前半導體的製程技術在發展上於2D封裝中已面臨技術邊緣，無法靠現有的技術來解決高速、大容量資訊的傳輸等問題。而3D封裝技術除了把水平的配線改為垂直貫穿通孔的配線外，其I/O數也遠比傳統技術的I/O數多，可想而知在未來即將被3D封裝的需求所取代。
　　歸納目前的研究結果顯示，有相當多文獻都在探討有機添加劑形成超級填孔(Superfilling)的機制，但是其電鍍後的結構皆為V形。根據吾人的研究發現，不同的型態會影響電鍍的結果，當表面為V形之型態時，則在孔中央會較有機會產生空洞或隙縫。如能以U形之型態出現則可以避免有隙縫或空洞的產生。本文的研究重點即在於開發一新穎電鍍銅的配方，能夠將矽通孔(Through Silicon Via，TSV)以超級填充的方式填充，又能以U形之型態完成填孔，以達到無隙縫和空洞理想沉積行為。在此篇文章中，電鍍完成後，所有的剖面圖都利用金相顯微鏡(optical microscope, OM)來觀察。另外使用電化學分析方法來分析添加劑，利用不同轉速的旋轉工作電極來摸擬在晶圓周遭的流場。
　　在研究過程中發現，當SPS與PA此兩者添加劑一起加入後，即可以產生吾人想要的U形電鍍形態。而當以U形電鍍形態來填孔時，在其底部上移(bottom-up)的過程猶如電梯上升一般，即在填充的過程中銅都是以平台的形態層層堆疊上升填孔，而在側壁的部分則是呈現幾乎不長銅的狀態。因此這新穎的填孔模式與傳統拉鍊式的填孔模式截然不同。最後吾人成功地將孔徑20μm、孔深70μm，深寬比為3.5的孔，以U形之形態且無空洞或隙縫之結構完整填充。再者，根據電鍍結果顯示，吾人判定PEG是提高良率的關鍵。當吾人使用PAA來取代原本的抑制劑時，發現改良後的配方可以用來填充高深寬比的孔。最後，吾人嘗試將小分子量的PEG(400)與PAA取代原本的抑制劑後，發現其良率確實提高了不少，而目前較有把握填充的深寬比為6.2。

The development of science and technology continuously progresses. Electronic components increasingly become small, thin, short and light. The evolution of semiconductor technology has reached a point where the packaging now plays an important role in the overall performance of the IC devices. There are some bottlenecks of two-dimensional (2D) packaging, which include size, speed, and volume of electronic packages. 3D packaging technology not only change horizontal interconnect techniques to vertical ones but also increase counts of input and output (I/O). Thus, 3D technology will replace 2D technology in the future.
　　Many articles have reported different plating formulas that are capable of forming superfilling. However, the top surface profile of the copper deposit inside the TSV always is V-shaped. According to our research, different top surface profiles of the copper deposits inside the TSV might cause different filling results. If the top surface profile of the copper deposit inside the TSV is V-shaped it has a risk to form a seam or a small void in the filled TSV. Another plating process will form a U-shaped profile at the top of the TSVs during plating, the plating process can make sure of no void and seam formation during plating. This paper is focused on development of a novel copper electroplating formula for filling TSV and this formula can lead to the top surface profile of the copper deposit inside the TSV to be U-shaped.
　　In this study, filling performance of the novel plating formula was evaluated by examining cross-section of the filled TSVs using an optical microscope (OM). The effects of chemical and physical interactions between the plating additives and fluid dynamics were characterized by using a potentiostat with a three-electrode cell. We used two rotation speeds of working electrode (WE) to simulate the fluid motion around the wafer. One was fixed at 1000 rpm to simulate the fluid motion outside the TSV. The other was fixed at 100 rpm to simulate the fluid motion inside the TSV. Electrochemical analyses show that the filling mechanism obey a model of convection-dependent adsorption (CDA) behavior.
　　The U-shape copper plating formula led to the bottom-up behavior looking like the motion of an elevator. That is, the top surface profile of the copper deposit filled in the TSV always was a flat plane during plating. Besides, the sidewall shrinkage due to copper deposition was insignificant during plating. This filling behavior is totally different from that of a conventional copper plating formula for via filling, which usually behaves a zipper-type filling mode and thus causes a seam formation at the center of the filled TSV. This invention of this work can make sure of no void and seam in the filled TSV with an aspect ratio of 3.5, where the diameter is 20 μm and the depth is 70 μm. Thus, the reliability of the TSV can be greatly improved. According to the plating results, we considered that the suppressor is the key point to improve yield. In our research, different suppressors might cause different filling results. After we tried using PAA to replace PEG, the new formula could filling high aspect-ratio vias but the plating results were not uniform. Finally, both yield and the capability of filling high aspect-ratio vias had improved after we tried using the suppressors of PEG(400) and PAA.

第一章、 緒論 ...........................................1
第二章、 理論文獻回顧 .....................................2
第一節、 銅製程 .........................................2
第二節、 電鍍 ...........................................4
第三節、 3D 晶片堆疊發展 ..................................6
第四節、 矽通孔(Through Silicon Vias, TSVs) ..............8
第五節、 電鍍溶液與添加劑 .................................11
第六節、 基礎電化學原理 ...................................31
第七節、 電鍍填充模擬理論 .................................33
第三章、 研究動機 .........................................38
第四章、 藥品與實驗裝置、步驟 ...............................39
第一節、 實驗藥品 ........................................39
第二節、 實驗裝置 ........................................40
第三節、 實驗步驟 ........................................48
第五章、 實驗結果與討論 ....................................50
第一節、 新穎平整劑的開發 .................................50
第六章、 結論 ............................................80
第七章、 未來研究項目 ......................................82
第八章、 參考文獻 .........................................84

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