臺灣博碩士論文加值系統

本論文是探討使用標準互補式金氧半製程來設計應用於光傳送器之鎖相迴路時脈產生器，它可產生數個互相呈倍數的時脈給多工器去合成平行傳輸的資料成一個高速串列的資料束。本文分別針對相關電路之設計、模擬、量測來說明。
首先，為了分析鎖相迴路時脈產生器，我們建立了迴路的參數並探討這些參數對鎖相迴路暫態響應的影響。此外，我們也注入雜訊到這個迴路，探討它與迴路參數的關係。
第二，我們設計出1GHz的鎖相迴路時脈產生器，模擬出其抖動為4.081ps rms，而且此電路的佈局面積只佔0.784mm × 0.653mm。我們的鎖相迴路時脈產生器有三個特色: (一)、可消除相頻偵測器輸出的脈衝雜訊(Glith)。(二)、為了達到高速的操作，振盪器僅由兩個延遲電路所組成。(三)、修改傳統的 TSPC反及閘之D型正反器(True-Single-Phase-Clock D type flip-flop with NAND gate)，以實現一個快速及無脈衝雜訊之電路架構於除頻器內。
第三，雖然整個鎖相迴路晶片尚未整合完成，但已經實現部份其組成之分系統，如擁有電荷消除功能的電荷幫浦、傳輸閘型的振盪器以及具有自我校正頻率功能的振盪器。而量測結果顯示這個具有自我校正頻率功能的振盪器之頻率可調範圍為204MHz至652MHz，並且它在±10%電源電壓變動範圍內，控制電壓分別從3V變化到1.6V，所對應之頻率誤差都在±4.3%內。
最後，為了提升振盪器之操作速度，我們實現了一個互補式LC tank壓控振盪器。振盪器操作頻率的量測值可從2.04GHz變化到2.51GHz，而且相位雜訊為-100dBc/Hz@1MHz。

This thesis describes a design of PLL clock generator for optical transmitter in a standard CMOS process. It can produce multiple-times clocks for a multiplexer which combines the parallel sequences of data at lower rates to generate a single high-speed serial signal. Our design methodology, simulation, and measurement can be summarized as follows.
First, in order to analyze the PLL clock generator, we have established the loop parameters. The parameters effect on the PLL transient characteristic has been studied. Besides, noise sources were introduced into the PLL and its relationship with the loop parameters was explored.
Second, a 1GHz PLL clock generator has been designed. The simulated jitter performance at 1GHz is equal to 4.081ps rms. The circuit only occupies an area of 0.784mm × 0.653mm. Furthermore, our PLL clock generator has three features. (i) A removal glitch circuit was presented to eliminate the coincident output pulse of the PFD. (ii) The ring oscillator consists of two delay cells and it enables a high-frequency operation. (iii) By modifying a traditional TSPC D-FF (True-Single-Phase-Clock D type flip-flop) with NAND gate, a fast and glitch-free TSPC D-FF with NAND gate was designed in the prescaler.
Third, although a single-chip system of PLL clock generator has not been completed, we have implemented some of the component subsystems such as the charge pump with charge removal, the transmission-gate VCO, and the self-regulating VCO. The measured self-regulating VCO exhibits a tuning range between 204MHz and 652MHz. Furthermore, it has better frequency immunity to supply voltage variation for the supply range of VDD ±10%. In the range of the control voltage from 3V to 1.6V, its frequency deviation is within ±4.3%.
Finally, a complementary type LC oscillator was implemented in order to improve a higher operating frequency. The measured LC oscillator has a tuning range of 2.04GHz to 2.51GHz. The phase noise at a 1MHz offset is approximated equal to -100dBc/Hz.

Chapter 1 Introduction
1.1 Motivation
1.2 Optic-Fiber Transceiver
1.3 Thesis Organization
Chapter 2 Analysis of Phase-Locked Loop clock generator
2.1 Basic PLL clock generator Topology
2.2 PLL loop dynamics
2.3 Jitter in PLLs
Chapter 3 A design of Phase-Locked Loop clock generator
3.1 Phase/Frequency Detector (PFD)
3.2 Charge Pump
3.2.1 Charge pump with charge removal
3.2.2 Charge pump with NMOS switches only
3.3 Loop Filter
3.4 Ring Oscillators
3.4.1 Transmission-Gate VCO
3.4.2 Self-regulating VCO (SR-VCO)
3.4.3 Two-stage VCO
3.5 Multi-modulus prescaler
3.6 Simulation result of a PLL clock generator
Chapter 4 Measurement results of clock generator
4.1 Charge pump with charge removal
4.2 Transmission-gate VCO
4.3 Self-regulating VCO
Chapter 5 Design and measurement of a 2.4GHz LC oscillator
5.1 Analysis of a LC oscillator
5.2 Design of a 2.4GHz complementary type LC oscillator
5.3 Measurement result of a 2.4GHz complementary type LC oscillator
Chapter 6 Conclusions and future work
6.1 Conclusions
6.2 Future work
Bibliography
Biography

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