臺灣博碩士論文加值系統

近幾年來最熱門的封裝技術之一為晶圓級扇出型封裝 (Fan-out Wafer Level Package；FOWLP)製程，這是因為此封裝技術是被認為將能夠輔助半導體技術跨越摩爾定律的瓶頸，同時也給晶圓代工業者跨入封裝製程的機會。然而目前FOWLP在製程上所面臨的挑戰是模封、晶片、載板間熱脹係數(Cofficient of Thermal Expanding；CTE)的不匹配對產品結構產生應力所引發再製程過程中翹曲 (warpage) 問題。本研究將模擬FOWLP各製程階段所產生的翹曲大小，並於結構中加入新設計之矽環(ring)結構，目的是希望此矽環能夠降低製程中所產生的翹曲量。為此，本研究將利用田口式實驗設計法來設計多樣的因子組合中來探討矽環結構尺寸和材料搭配對FOWLP製程上所產生的翹曲的影響，並透過此方法找出最佳的因子組合設計，以求有效的降低製程上所產生的翹曲量。由於此新設計之矽環並未於以往文獻有所提及，故本研究提出之有效降低FOWLP製程上所產生的翹曲量的方法與建議，並可對相關產業有所幫助。

Fan-out wafer level package (FOWLP) is one of most popular packaging technology in recent years. This is because FOWLP is considered as the key to break through the bottleneck of Moore’s Law, and it provides opportunities for the foundries to participate packaging business. However, FOWLP process is facing the challenges on packaging warpage during manufacturing process due to CTE mismatch between the structure materials. To this end, FOWLP warpage in each process stages were simulated, and a new silicon ring design was proposed to reduce process warpage in this study. To reduce warpages in FOWLP process, Taguchi Methods with different variables were uses to study the optimal factorial combinations on material properties and ring designs. With the results of this study and the new silicon ring designs, warpages on FOWLP process have been effectively reduced and useful information were provided to the packaging industry.

目錄 V
表目錄 VII
圖目錄 VIII
符號說明 X
1. 緒論 1
1.1 前言 1
1.2 扇出型晶圓級封裝 2
1.3 研究動機與目的 5
1.4 文獻回顧 5
1.5 論文架構 13
2. 理論分析 14
2.1 熱應力理論分析 14
2.2 等效材料分析 20
2.3 田口式實驗設計法 26
2.4.1 實驗設計因子 26
2.4.2 直交表 27
2.4.3 信號雜訊比 29
3. 研究方法之模擬與田口式實驗設計 31
3.1研究方法 31


3.1.1 模擬方法 32
3.1.2 田口式實驗設計法流程 37
4. 結果與討論 40
4.1 模擬驗證 40
4.2 FOWLP製程模擬結果 42
4.3 最佳化分析與模擬結果 44
5. 結論 50
6. 參考文獻 52

[1]Che, F. X., Hu, D., Ding, M. Z., and Zhang, X., “Modeling and design solutions to overcome warpage challenge for Fan-out wafer level packaging (FO-WLP) technology,” in Proc. IEEE EPTC, pp. 2–4, Dec. 2015.
[2]Che, F. X., Hu, D., Ding, M. Z., and MinWoo, D. R., “Study on process induced wafer level warpage of fan-out wafer level packaging,” in Proc. IEEE ECTC pp., 1879–1885, May 2016.
[3]Timoshenko, S.P., “Analysis of bi-metal thermostats,” J.Opt. Soc. Am., vol. 11, no. 3, pp. 233–255, 1925.
[4]Lau, J. H., et al., “Warpage and thermal characterization of fan-out waferlevel packaging,”IEEE Trans. Compon., Packag., Manuf. Technol.,vol. 7,Isuue: 10, , pp. 1729–1738, Oct. 2017.
[5]Lau, J. H., et al., “Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 8, Issue: 10, pp. 1729–1737, July 2018.
[6]Hu, G. J., Yong, G. K., and Lim, J., “Micromechanical analysis of copper trace in printed circuit boards,” Microelectron. Rel., vol. 51, pp. 416–424, Feb. 2011.
[7]Hou, F., Lin, T., Cao, L., Liu, F., Li, J., Fan, X., and Zhang, G. Q. ,“Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package,” IEEE Trans. Compon., Packag., Manuf. Technol., Vol. 7, Issue: 10, pp. 1721-1728, Aug. 2017.
[8]張勳承，“田口方法應用於覆晶構裝錫球的熱應力分析”，碩士論文，國立成功大學機械工程學系，台南，第57-61頁，2003。
[9]王玟婷，“封裝材料對電子封裝翹曲之影響”，碩士論文，國立交通大學機械工程學系，新竹，2015。
[10]Ge, Z., and Wang, K., “Optimization of structure for BGA packaging based on Taguchi method,” International Conference on Electronic Packaging Technology (ICEPT), China, pp. 1433-1437. Aug. 2015.
[11]Xia, J., Li, G. Y., and Lin, B., “Optimal Design for Vibration Reliability of Package-on-Package Assembly Using FEA and Taguchi Method,” IEEE Trans. on Components, Packaging and Manufacturing Technology, Vol. 6, Issue 10, pp. 1482-1487, 2016.
[12]Rodrigo, A., “Enabling of fan-out WLP for more demanding applications by introduction of enhanced dielectric material for higher reliability,” in Proc. IEEE ECTC, pp. 935–939, May 2014.
[13]Tseng, C., Liu, C., Wu, C., and Yu, D., “InFO (wafer-level integrated fan-out) technology,” in Proc. IEEE ECTC, pp. 1–6, May 2016.
[14]Hsieh, C., Wu, C., and Yu, D., “Analysis and comparison of thermal performance of advanced packaging technologies for state-of-the-art mobile applications,” in Proc. IEEE ECTC, pp. 1430–1438, May 2016.
[15]Chang, H. D., Chang, D., Liu, K., Hsu, H. S., Tai, R. F., and Huang, H.C., “Development and characterization of new generation panel fan-out (P-FO) packaging technology,” ECTC 64th , Orlando, FL, USA, pp. 947–951, Sep. 2014.
[16]Liu, H. W., Liu, Y. W., and Ji, Jason, Liao,Jash, Chen, Agassi, Chen, Y. H., Kao, Nicholas, and Lai, Y. C., “Warpage Characterization of Panel Fan-out (P-FO) Package,” ECTC 64th , Orlando, FL, USA, pp. 1750-1754, Sep. 2014.
[17]Tsai, S. W., Hahn, and H. T., “Introduction to Compsite Materials,” TECHNOMIC Publishing Co., Inc. 1980 265 Post Road West, Westport, pp. 379-394,1985.
[18]李輝煌，“品質工程線外方法與應用”，前程文化事業有限公司，新北市，2015。