臺灣博碩士論文加值系統

在過去3D圖形繪圖一般是應用在桌上型電腦或是遊戲主機上，但是由於目前手持系統，例如：智慧型手機、個人數位助理(PDA)、筆記型電腦等，在一般生活中的使用越來越廣泛，所以3D圖形繪圖應用也就帶入了手持系統中。一般而言3D圖形繪圖需要複雜的運算，而手持系統不如一般的桌上型電腦或是遊戲主機有強大的運算能力。此外，手持系統的電源供應來自於電池，不像桌上型電腦或是遊戲主機是使用外接電源。再者，目前製程發展依照莫爾定理(Gordon Moore)：每18個月左右晶片單位面積中所包含的電晶體數將會增加一倍，雖然製造成本下降，可是電池容量卻無法隨著電晶體數同步成長。因此，如何在手持系統中增加電源管理機制以達到低功率省電的效果，已成為三維圖形繪圖系統設計上一個極重要的研究課題。

對於3D圖形繪圖而言，目前廣泛使用的電源管理機制為動態電壓及頻率調整(DVFS)，因此如何準確的預測及調整電壓與頻率也就成為許多相關文獻的研究方向。目前已知的預測方式可分為History-based predictor [1]和Frame-structure predictor [2-4]。History-based predictor是由先前畫面的工作量來預測之後畫面的工作量並調整電壓，而Frame-structure predictor是在offline先做分析並將application大致分為不同種類的畫面，然後儲存成表格與對應的電壓值，再依照目前畫面的種類來查表進而調整電壓。許多的研究者是將電源管理機制放置在軟體(中央處理器)之中，而我們則是將電源管理的機制另外設計成為硬體，這樣不只可以節省手持系統中處理器的運算量，還可以更快速及準確的調整電壓及頻率值。而我們的預測方法可以歸類為History-based predictor的一種，是將PID (Proportional-Integral-Derivative) predictor [5-6]以動態的方式去調整Proportional控制器和Integral控制器的參數值，可以達到比非動態控制器更好的效果。
由於一般選擇到的電壓值可以處理的工作量會多於預測的工作量，或者是實際的工作量少於預測的工作量，這之間便會產生額外的閒置時間(Slack-time)，因此我們使用Inter-frame compensation [7-10]的方法來利用這些多餘的閒置時間，如此可以在不影響圖形影像的品質下節省更多的功率消耗。由於我們將電源管理裝置實現成硬體，所以採用較簡單的方式選出兩個參數以進行畫面和畫面之間的補償。實驗結果顯示混和了動態PID predictor以及動態Inter-frame補償的方法可以達到更為明顯的省電效果並且得到更準確的預測結果。

In the past few years, due to the rapid advance in technology and the aid of 3D graphics applications the world of 3D graphics is rapidly expanding from desktop computers and dedicated gaming consoled to handheld devices, such as cellular phones, PDAs, laptops etc.,. However, unlike traditional desktop computers and gaming consoles, mobile computing devices typically have slower processors that have less capability for handling large computation-intensive workloads like 3D graphics application. In addition, the power consumption is one of the major design specifications to realize the 3D graphics accelerating engine for mobile devices because handheld batteries have limited lifetimes. Moreover, the size of chip is depend on the Moore’s Law: The number of transistors in a chip are double in every eighteen months. Even though the produce cost is decrease, but the capacity of battery cannot increase like the transistors. Therefore, how to reduce power consumption by using efficient power management techniques has become a very important research topic in 3D graphics SoC design.

For 3D graphics applications, dynamic voltage and frequency scaling (DVFS) is a good candidate to reduce the power consumption of 3D graphics accelerating engine. So many relative papers have researched in how to accurately predict the workload and scale the voltage and frequency. The prediction policy can divide into History-based predictor [1] and Frame-structure predictor [2-4]. The History-based predictor predicts the latter frame workload by previous frame workload to scale the voltage, and the frame-structure predictor performs offline and then determine the different kind of frame for an application. A table is used to save the mapping of different kind of frame to the voltage, and then the voltage is scaled according to the mapping table. A lot of researchers put the power management policy in software i.e. processors, but our proposed workload prediction scheme has been realized into the hardware circuit. Therefore, it can not only reduce the overhead of processor but also quickly adjust the voltage and frequency of 3D graphics accelerating engine. Our prediction policy is one of the History-based predictor ,and it is an adaptive PID predictor [5-6] in which the parameters of Proportional controller and Integral controller can be adaptively adjusted so that it can obtain more accurate prediction results than non-adaptive predictor.

In general, the workload that the selected voltage can handle is usually over than the predicted workload. That is, actual workload is usually less than predicted workload. So that the slack time will be generated. We can utilize the slack time through Inter-frame compensation [7-10] to save more energy while maintaining the similar output quality. We use a simple policy to adaptively select the parameters for compensation between the frames to simplify the hardware architecture of the power management policy. Experimental results show that, we can get more energy saving and more accurate workload prediction when the adaptive PI predictor and adaptive Inter-frame compensation are utilized.

第一章 概論 1
1.1研究動機 1
1.2 論文大綱 3
第二章 研究背景與相關研究 4
2.1 電源管理策略簡介 4
2.2 低功率設計技術簡介 9
2.2.1時脈閘控(clock gating) 10
2.2.2運算元隔離 (Operand Isolation) 12
第三章 三維圖形系統晶片架構與電源管理方法 13
3.1 三維圖形系統晶片架構 13
3.2 電源管理方法 17
3.2.1 Buffer預測方法 18
3.2.2 Frame-based 預測方法 20
3.2.3 History-based 預測方法 23
3.2.4 比例-積分-微分 預測方法 24
3.3補償方法 28
3.3.1 Intra-frame 補償方式 29
3.3.2 Inter-frame 補償方式 32
3.3.3 Modify Voltage Frequency Mapping 34
第四章 混合型電源管理策略 35
4.1 動態調整PI預測方式 35
4.2 動態的PI調整方式和Modify Voltage Frequency Mapping 37
4.3 動態的PI調整方式和Inter-frame補償方式 38
4.3.1 原理 38
4.3.2 硬體電路 40
第五章 實驗環境設定與結果 44
5.1 C model 44
5.1.1 三維圖形系統流程 44
5.1.2 不同電壓對應的頻率值、消耗能量值 46
5.1.3 UW1_5介紹和其他相關參數定義 47
5.2 Benchmark 49
5.2.1 API benchmark 49
5.2.2 FPGA上的benchmark數據 52
5.3 C model simulation 之CPU 結果 53
5.3.1 Adaptive PI 53
5.3.2 Adaptive PI 加上補償方法 54
5.4 C model simulation 之FPGA 結果 56
5.4.1 Adaptive PI (假設電壓頻率) 56
5.4.2 Adaptive PI 加上補償方法 (假設電壓頻率) 57
5.4.3 Adaptive PI (StrongArm 110-based system) 58
5.4.4 Adaptive PI 加上補償方法 (StrongArm 110-based system) 59
5.4.5 Adaptive PI (XScale-based system) 61
5.4.6 Adaptive PI 加上補償方法 (XScale-based system) 62
5.5 Power Management 在CDK上實現的結果 64
5.6 Power Management加上Clock Generator 65
第六章 結論 67
參考文獻 68

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