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研究生:夏愈閎
研究生(外文):XIA,YU-HONG
論文名稱:高介電HfO2晶相及TiO2/HfO2堆疊結構之研究
論文名稱(外文):Study of HfO2 Crystal Phase and TiO2/HfO2 Stacked Structures for High Dielectric
指導教授:陳世志陳世志引用關係
指導教授(外文):Chen Shih-Chih
口試委員:曾憲正張守進
口試委員(外文):Zeng Xian-ZhengZhang Shou-Jin
口試日期:2018-07-20
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:103
中文關鍵詞:射頻磁控濺鍍二氧化鉿二氧化鈦晶相轉變鈦覆蓋層氮化鈦電極
外文關鍵詞:RF magnetic sputterHfO2TiO2Phase transitionTi-capping layerTiN gate electrode
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本研究針對TiN/Ti/ HfO2/TiO2/HfO2/Si結構,利用二氧化鉿-二氧化鈦-二氧化鉿薄膜閘極堆疊來探討結構中的電特性。
本實驗利用射頻磁控濺鍍系統在p型矽基板[1~5 Ω-cm (100)]上沉積三層高介電材料,沉積二氧化鉿與二氧化鈦薄膜當作介電層,利用不同的二氧化鉿與二氧化鈦薄膜厚度做為比較,之後在薄膜上沉積一層Ti-capping layer以及氮化鈦閘極電極,沉積完成後進行不同溫度和時間的Ti-cap PDA處理。
本實驗主要在薄膜沉積過程探討幾種情況,分別為二氧化鉿與二氧化鈦薄不同薄膜厚度下的影響,以及不同時間Ti-cap PDA下的晶相轉變退火溫度的不同,來找出最佳的高介電值、界面情形與漏電流的影響,並探討閘極氧化層的物理、電特性、缺陷以及漏電流機制,找出最佳條件後製作成MOS電容。
由實驗可得知,Ti-cap PDA達到750度時,有助於非晶二氧化鉿薄膜形成穩定的四方晶相,而二氧化鈦也從非晶相轉成穩定的金紅石相,並且有效地抑制二氧化矽介面層的生長。

In this study, the structure of TiN/Ti/HfO2/TiO2/HfO2/Si was studied by using a titanium dioxide and hafnium oxide film gate stack to investigate the electrical properties of the structure.
In this experiment, three layers of high dielectric materials were deposited on a p-type silicon substrate [1~5 Ω-cm (100)] using RF magnetron sputtering system. The HfO2 and TiO2 films were deposited as dielectric layers. The thickness of hafnium dioxide was compared with the thickness of titanium dioxide film. After that, a Ti-capping layer and titanium nitride gate electrode were deposited on the film. Ti-cap
PDA treatment with different temperatirs and times was performed after deposition.
The experiment investigates in the film deposition process. They are the effect of different thickness of hafnium and titania and the difference in the annealing temperature of the crystal phase at different times of Ti-cap PDA to find the best the influence of high dielectric value, interface conditions and leakage current is discussed.
The physical, electrical characteristics, defects, and leakage current mechanism of
the gate oxide layer are also discussed. After finding the best conditions, a MOS capacitor is fabricated.
From the experiments, it can be seen that when the Ti-cap PDA reaches 750 degrees, it contributes to the formation of a stable tetragonal crystal phase of the amorphous ceria film, and the titanium dioxide also changes from the amorphous crystal phase to a stable rutile phase, and is effective suppresses the growth of the SiO2 interface layer.

目錄
摘要 i
ABSTRACT ii
致謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章、 緒論 1
1-1 研究背景 1
1-1-1 電晶體的歷史 2
1-1-2 MOS製程技術之發展 4
1-1-3 高介電常數(high-k)材料的選擇 6
1-2 研究方法 8
1-3 論文架構 9
第二章、 基礎理論及文獻回顧 17
2-1 基礎理論 17
2-1-1 電容(Capacitor)與等效氧化層厚度(EOT) 17
2-1-2 MOS電容結構與理想C-V特性 18
2-1-3 影響理想MOS電容C-V特性之氧化層缺陷型態 20
2-1-4 氧化層缺陷對遲滯曲線方向的影響 24
2-1-5 界面與氧化層陷阱密度(interface trap density, Nit / Oxide charge density, Not ) 25
2-1-6 射頻磁控濺鍍(RF Magnetron Sputtering) 25
2-1-7 退火(Annealing) 26
2-1-8 漏電流機制 27
2-2 文獻回顧 34
第三章、 實驗步驟 48
3-1 實驗步驟簡介 48
3-1-1 Si基板之化學清洗 48
3-1-2 濺鍍系統與高介電薄膜沉積 49
3-1-3 Ti-capping layer沉積 49
3-1-4 TiN gate electrode沉積 50
3-1-5 不同條件之Ti-capping layer事後沉積退火(Ti-capping layer Post Deposition Annealing, Ti-cap PDA) 50
3-1-6 製備MOS電容 50
3-2 物性量測 51
3-2-1 掠角X光繞射儀(Grazing Incident X-ray Diffraction, XRD) 51
3-3 電性量測 52
3-3-1 I-V量測 52
3-3-2 C-V量測 52
第四章、 結果與討論 60
4-1 不同溫度及時間之Ti-cap PDA處理對結晶狀態之探討 60
4-1-1 XRD分析 61
4-2 以11nm不同溫度之Ti-cap PDA 處理元件電性之探討…………….61
4-2-1 電性分析…………………………………………………..........61
4-2-2 EOT V.S Jg....................................................................................63
4-3 漏電流機制分析………………………………………………… …… 63
4-3-2 實驗結果分析…………………………………………..………63
第五章、 結論與未來研究方向………………………………… ………………82
5-1 結論……………………………………………………………………82
5-2 未來研究方向…………………………………………………………83
參考文獻 84




















表目錄
表1-1 半導體元件發展時間和順序 10
表1-2 尺寸縮小的趨勢 11
表1-3 各種高介電材料相關特性之比較 11
表1-4 HfO2不同晶相之平均介電常數 12
表1-5 TiO2不同晶相之介電常數 12
表3-1 HfO2薄膜沉積條件 54
表3-2 TiO2薄膜沉積條件 54
表3-3 HfO2薄膜沉積條件 54
表3-4 Ti-capping layer沉積條件 55
表3-5 TiN薄膜沉積條件 56
表3-6 Al下電極沉積條件 56
表3-7實驗與量測儀器 57
表4-1 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si堆疊結構HfO2/TiO2/HfO2為11 nm 不同時間下 700℃Ti-cap PDA之數據整理…………………………………….66
表4-2 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si堆疊結構HfO2/TiO2/HfO2為11 nm
不同時間下 750℃Ti-cap PDA之數據整理…………………………………….66
表4-3 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si堆疊結構HfO2/TiO2/HfO2為11 nm
不同時間下 800℃Ti-cap PDA之數據整理…………………………………….67
表4-4 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si堆疊結構HfO2/TiO2/HfO2為11 nm
不同時間下 850℃Ti-cap PDA之數據整理…………………………………….67
表4-5 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si堆疊結構HfO2/TiO2/HfO2為11 nm
不同時間下 900℃Ti-cap PDA之數據整理…………………………………….68











圖目錄
圖1-1摩爾定律(Moore's Law)的演變 13
圖1-2 Intel技術發展推進趨勢 13
圖1-3使用High-k材料作為閘極氧化層和金屬閘極的金氧半場效電晶體 14
圖1-4載子遷移率對場效電晶體垂直電場的示意圖 14
圖1-5 Planar FDSOl與SOI FinFET 和Bulk FinFET結構示意圖 15
圖1-6各種高介電材料介電常數與能帶之關係 15
圖1-7矽與氧化層的能帶偏移示意圖 16
圖1-8各種高介電材料與矽基板的能障接合高度 16
圖2-1基本MOS電容之 (a)透視圖 (b)截面圖 36
圖2-2 V=0時理想MOS電容之能帶圖 36
圖2-3聚積時理想MOS電容之能帶圖與電荷分佈圖 37
圖2-4空乏時理想MOS電容之能帶圖及電荷分佈圖 37
圖2-5反轉時理想MOS電容之能帶圖及電荷分佈圖 38
圖2-6 MOS電容之等效電路圖 38
圖2-7理想p-type MOS電容電壓曲線 39
圖2-8 p-type MOS電容在高、低頻率下之理想C-V圖 39
圖2-9 SiO2之相關缺陷電荷分佈 40
圖2-10界面陷阱電荷對MOS電容電壓特性曲線的影響(a)高頻(b)低頻 40
圖2-11 p-type MOS電容固定氧化層電荷之高頻電容對閘極電壓曲線影響 41
圖2-12 (a)理想MOS電容之C-V特性曲線。(b)由於正的固定氧化層電荷,造成曲線沿著電壓軸平行位移。(c)由於界面陷阱電荷,造成曲線沿著電壓軸非平行位移。 41
圖2-13可移動金屬離子造成電遲滯曲線的效應 42
圖2-14氧化層內電荷造成電遲滯曲線的效應 42
圖2-15 Barrier limited 傳導機制;(a)Schottky emission、(b) Tunneling 43
圖2-16 Bulk limited 傳導機制;(a) 空間電荷限制傳導、(b) 離子傳導、(c) Poole-Frenkel emission 43
圖2-17載子在絕緣體的電流傳導機制 (a)膜厚的場合、(b)膜薄的場合、(c)膜極薄的場合 44
圖2-18 (a) 在金屬與介電層的接面結構中影像電荷與電力線示意圖 46
(b) 在無外加電場下由於影像電荷所造成的能位障改變 46
(c) 在一固定外加電場下由於影像電荷所造成的能位障降低 46
圖2-19 Poole-Frenkel內部蕭基效應在金屬絕緣層半導體的MIS結構的示意圖 43
圖2-20 Fowler-Nordheim Tunneling在金屬絕緣層半導體的MIS結構的示意圖 44
圖3-1 TiN/Ti-capping layer/HfO2/ TiO2/ HfO2/P-type Si堆疊結構晶相轉變示意圖57
圖3-2 RF磁控濺鍍機示意圖(SPF-210H) 58
圖3-3 Shadow Metal Mask圖案 58
圖3-4實驗流程圖 59
圖4-1 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在700℃不同時間PDA之XRD圖 69
圖4-2 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在750℃不同時間PDA之XRD圖 69
圖4-3 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在800℃不同時間PDA之XRD圖 70
圖4-4 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在850℃不同時間PDA之XRD圖 70
圖4-5 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在900℃不同時間PDA之XRD圖 71
圖4-6 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在700℃不同時間PDA之I-V圖 71
圖4-7 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在750℃不同時間PDA之I-V圖 72
圖4-8TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在800℃不同時間PDA之I-V圖 72
圖4-9 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在850℃不同時間PDA之I-V圖 73
圖4-10 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在900℃不同時間PDA之I-V圖 73
圖4-11 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在700℃不同時間PDA之C-V圖 74
圖4-12 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在750℃不同時間PDA之C-V圖 74
圖4-13TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在800℃不同時間PDA之C-V圖 75
圖4-14 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在850℃不同時間PDA之C-V圖 75
圖4-15TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si閘極結構在900℃不同時間PDA之C-V圖 76
圖4-16閘級堆疊結構與其他作者比較之EOT vs Jg…………………………………76
圖4-17 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm時750℃-3sec、900℃-3sec PDA之Schottky Emission電流機制關係….……77
圖4-18 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
時750℃-3sec PDA之Schottky Emission電流機制關係………………………77
圖4-19 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
時900℃-3sec PDA之Schottky Emission電流機制關係………………………78
圖4-20 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
時750℃-3sec 、900℃-3sec PDA之Poole-Frenkel Emission電流機制關係….78
圖4-21 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
時750℃-3sec PDA之Poole-Frenkel Emission電流機制關係………………….79
圖4-22 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
時900℃-3sec PDA之Poole-Frenkel Emission電流機制關係………………….79
圖4-23 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
750℃-3sec、900℃-3sec PDA之Fowler-Nordheim tunneling電流機制關係…80
圖4-24 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
750℃-3sec PDA之Fowler-Nordheim tunneling電流機制關係………………80
圖4-25 TiN/Ti-capping layer/ HfO2/TiO2/HfO2/p-Si為HfO2/TiO2/HfO2堆疊結構11nm
900℃-3sec PDA之Fowler-Nordheim tunneling電流機制關係…………… ...81









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